ISL6420BEVAL1Z Intersil, ISL6420BEVAL1Z Datasheet - Page 5

• Manufacturer Part Number: ISL6420BEVAL1Z
• Description: EVAL BOARD 1 FOR ISL6420B
• Manufacturer: Intersil

Specifications of ISL6420BEVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Voltage Margining
Voltage margining mode is enabled by connecting a
margining set resistor (R6) from the VMSET pin to
ground. This resistor to ground will set a current, which is
switched to the FB pin. The current will be equal to
2.468V divided by the value of the external resistor tied
to the VMSET pin. The range of the VMSET resistor is
150kΩ to 400kΩ.
The GPIO1 (TP4) and GPIO2 (TP5) pins control the
current switching as per Table 3. The power supply
output increases when GPIO2 is HIGH and decreases
when GPIO1 is HIGH. Using a jumper to short the pins of
JP1 and JP2 will pull GPIO1 and GPIO2 LOW, respectively.
Remove one of the jumpers to pull GPIO1 or GPIO2 HIGH
for voltage margining. The amount that the output
voltage of the power supply changes with voltage
margining will be equal to 2.468V times the ratio of the
external feedback resistor (R1) and the external resistor
tied to VMSET (R6).
The evaluation board has a 330kΩ VMSET resistor (R6)
setting a current:
and:
The slew time of the current is set by an external
capacitor (C13) on the CDEL pin, which is charged and
discharged with a 100µA current source. The change in
voltage on the capacitor is 2.5V. This same capacitor is
also used to set the PGOOD rise delay. When PGOOD is
low, the internal PGOOD circuitry uses the capacitor and
when PGOOD is high the voltage margining circuit uses
the capacitor. The slew time for voltage margining can be
in the range of 300µs to 2.5ms. The CDEL capacitor on
the evaluation board is 0.1µF leading to a voltage
margining slew rate of 2.5ms. Figures 15 and 16 show
negative and positive voltage margining with a CDEL
capacitor of 0.1µF.
I
V Δ ( )
VM
=
=
GPIO1
2.468V 330kΩ
7.48μA 11.5kΩ
H
H
L
L
⁄
•
=
7.48μA
=
0.086V
TABLE 3.
GPIO2
5
H
H
L
L
Application Note 1504
No Change
+Δ V
-Δ V
Ignored
V
OUT
OUT
OUT
(EQ. 3)
(EQ. 4)
FIGURE 15. NEGATIVE VOLTAGE MARGINING SLEW
FIGURE 16. POSITIVE VOLTAGE MARGINING SLEW
CDEL
GP101
V
GPIO2
GPIO1
GP102
V
CDEL
OUT
OUT
TIME
TIME
V
V
IN
IN
= 18V, V
= 18V, V
OUT
OUT
= 3.3V, NO LOAD
= 3.3V, NO LOAD
November 23, 2009
AN1504.0