LP3906SQ-JXXIEV/NOPB National Semiconductor, LP3906SQ-JXXIEV/NOPB Datasheet - Page 20
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LP3906SQ-JXXIEV/NOPB
Manufacturer Part Number
LP3906SQ-JXXIEV/NOPB
Description
EVAL BOARD FOR LP3906SQ-JXXI
Manufacturer
National Semiconductor
Datasheet
1.LP3906SQ-DJXINOPB.pdf
(40 pages)
Specifications of LP3906SQ-JXXIEV/NOPB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (5Mb)
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t
t
t
t
1
2
3
4
Symbol
LP3906 Default Power-Off Sequence
Note: LP3906 The default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or 10 ms. Default setting is the same as the on sequence.
Power-On-Reset
The LP3906 is equipped with an internal Power-On-Reset
(“POR”) circuit that will reset the logic when VDD < V
guarantees that the logic is properly initialized when VDD ris-
Programmable Delay from EN_T deassertion to V
Programmable Delay from EN_T deassertion to V
Programmable Delay from EN_T deassertion to V
Programmable Delay from EN_T deassertion to V
Description
POR
. This
CC
CC
CC
CC
_Buck1 Off
_Buck2 Off
_LDO1 Off
_LDO2 Off
20
es above the minimum operating voltage of the Logic and the
internal oscillator that clocks the Sequential Logic in the Con-
trol section.
Min
Typ
1.5
2
3
6
Max
20197811
Units
ms
ms
ms
ms
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