LP3906SQ-JXXIEV/NOPB National Semiconductor, LP3906SQ-JXXIEV/NOPB Datasheet - Page 21

• Manufacturer Part Number: LP3906SQ-JXXIEV/NOPB
• Description: EVAL BOARD FOR LP3906SQ-JXXI
• Manufacturer: National Semiconductor

Specifications of LP3906SQ-JXXIEV/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
I
The LP3906 features an I
two dedicated pins: SCL and SDA for I
spectively. Both signals need a pull-up resistor according to
the I
is clocked by the incoming SCL clock.
I
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as the SDA sig-
nal transitioning from HIGH to LOW while the SCL line is
HIGH. STOP condition is defined as the SDA transitioning
from LOW to HIGH while the SCL is HIGH. The I2C master
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledged related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying acknowledgement.
A receiver which has been addressed must generate an ac-
knowledgement (“ACK”) after each byte has been received.
After the START condition, the I2C master sends a chip ad-
dress. This address is seven bits long followed by an eighth
2
2
2
C SIGNALS
C START AND STOP CONDITIONS
C Compatible Serial Interface
2
C specification. The LP3906 interface is an I
2
C compatible serial interface, using
2
C clock and data re-
2
START and STOP Conditions
C slave that
I
2
C Signals: Data Validity
I
2
C Chip Address
21
Signal timing specifications are according to the I
ification. The maximum bit rate is 400 kbit/s. See I
cation from Philips for further details.
I
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL), e.g.- the state of the data line
can only be changed when CLK is LOW.
always generates START and STOP bits. The I2C bus is
considered to be busy after START condition and free after
STOP condition. During data transmission, I2C master can
generate repeated START conditions. First START and re-
peated START conditions are equivalent, function-wise.
bit which is a data direction bit (R/W). Please note that ac-
cording to industry I2C standards for 7-bit addresses, the
MSB of an 8-bit address is removed, and communication ac-
tually starts with the 7th most significant bit. For the eighth bit
(LSB), a “0” indicates a WRITE and a “1” indicates a READ.
The second byte selects the register to which the data will be
written. The third byte contains data to write to the selected
register.
LP3906 has a chip address of 60’h, which is factory pro-
grammed.
2
C DATA VALIDITY
20197818
20197816
20197817
2
www.national.com
C bus spec-
2
C specifi-