NUTINY-SDK-100 Nuvoton Technology Corporation of America, NUTINY-SDK-100 Datasheet - Page 54

• Manufacturer Part Number: NUTINY-SDK-100
• Description: BOARD EVALUATION NUC100 SERIES
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r
• Type: MCUr

Specifications of NUTINY-SDK-100

• Contents: Board, Cable
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: NUC100 Series

5.10 Watchdog Timer (WDT)
5.10.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports another function to wakeup CPU from power-down mode. The watchdog timer
includes a 18-bit free running counter with programmable time-out intervals. Table 5-2 show the
watchdog timeout interval selection and Figure 5-64 shows the timing of watchdog interrupt signal
and reset signal.
Setting WTE (WDTCR [7]) enables the watchdog timer and the WDT counter starts counting up.
When the counter reaches the selected time-out interval, Watchdog timer interrupt flag WTIF will
be set immediately to request a WDT interrupt if the watchdog timer interrupt enable bit WTIE is
set, in the meanwhile, a specified delay time (1024 * T
set WTR (WDTCR [0]) (Watchdog timer reset) high to reset the 18-bit WDT counter to avoid CPU
from Watchdog timer reset before the delay time expires. WTR bit is cleared automatically by
hardware after WDT counter is reset. There are eight time-out intervals with specific delay time
which are selected by Watchdog timer interval select bits WTIS (WDTCR [10:8]). If the WDT
counter has not been cleared after the specific delay time expires, the watchdog timer will set
Watchdog Timer Reset Flag (WTRF) high and reset CPU. This reset will last 63 WDT clocks
(T
cleared by Watchdog reset. User may poll WTFR by software to recognize the reset source. WDT
also provides wakeup function. When chip is powered down and the Watchdog Timer Wakeup
Function Enable bit (WDTR[4]) is set, if the WDT counter has not been cleared after the specific
delay time expires, the chip will be waken up from power down state.
RST
) then CPU restarts executing program from reset vector (0x0000_0000). WTRF will not be
WTIS
000
001
010
011
100
101
110
111
Timeout Interval
2
2
2
2
2
2
2
2
Selection
Table 5-2 Watchdog Timeout Interval Selection
10
12
14
16
18
4
6
8
T
* T
* T
* T
* T
* T
* T
* T
* T
TIS
WDT
WDT
WDT
WDT
WDT
WDT
WDT
WDT
Interrupt Period
1024 * T
1024 * T
1024 * T
1024 * T
1024 * T
1024 * T
1024 * T
1024 * T
T
- 54 -
INT
WDT
WDT
WDT
WDT
WDT
WDT
WDT
WDT
NuMicro™ NUC100 Data Sheet
WDT
Publication Release Date: Nov. 11, 2010
Min. T
341.33 us ~ 426.67 us
) follows the time-out event. User must
WTR Timeout Interval
(WDT_CLK=12 MHz)
21.33 us ~ 106.67 us
85.33 us ~ 170.67 us
21.84 ms ~ 21.93 ms
1.33 us ~ 86.67 us
5.33 us ~ 90.67 us
1.36 ms ~ 1.45 ms
5.46 ms ~ 5.55 ms
WTR
R
~ Max. T
WTR
Revision V2.00