NUTINY-SDK-100 Nuvoton Technology Corporation of America, NUTINY-SDK-100 Datasheet - Page 56

• Manufacturer Part Number: NUTINY-SDK-100
• Description: BOARD EVALUATION NUC100 SERIES
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r
• Type: MCUr

Specifications of NUTINY-SDK-100

• Contents: Board, Cable
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: NUC100 Series

5.11 UART Interface Controller (UART)
5.11.1 Overview
NuMicro™ NUC100 Medium Density provides up to three channels of Universal Asynchronous
Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform
Normal Speed UART, besides, only UART0 and UART1 support flow control function. NuMicro™
NUC100 Low Density only supports UART0 and UART1.
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data
transmitted from the CPU. The UART controller also supports IrDA SIR Function, LIN
master/slave mode function and RS-485 mode functions. Each UART channel supports seven
types of interrupts including transmitter FIFO empty interrupt (INT_THRE), receiver threshold
level reaching interrupt (INT_RDA), line status interrupt (parity error or framing error or break
interrupt) (INT_RLS), receiver buffer time out interrupt (INT_TOUT), MODEM/Wakeup status
interrupt (INT_MODEM), Buffer error interrupt (INT_BUF_ERR) and LIN receiver break field
detected interrupt (INT_LIN_RX_BREAK). Interrupts of UART0 and UART2 share the interrupt
number 12 (vector number is 28); Interrupt number 13 (vector number is 29) only supports
UART1 interrupt. Refer to Nested Vectored Interrupt Controller chapter for System Interrupt Map.
The UART0 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver FIFO
(RX_FIFO) that reduces the number of interrupts presented to the CPU and the UART1~2 are
equipped 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The CPU
can read the status of the UART at any time during the operation. The reported status information
includes the type and condition of the transfer operations being performed by the UART, as well
as 4 error conditions (parity error, framing error, break interrupt and buffer error) probably occur
while receiving data. The UART includes a programmable baud rate generator that is capable of
dividing clock input by divisors to produce the serial clock that transmitter and receiver need. The
baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and BRD are defined in
Baud Rate Divider Register (UA_BAUD). Table 5-3 lists the equations in the various conditions
and Table 5-4 list the UART baud rate setting table.
Mode
0
1
2
DIV_X_EN
0
1
1
Baud rate
921600
460800
230400
115200
DIV_X_ONE
Table 5-3 UART Baud Rate Equation
0
0
1
System clock = 22.1184MHz
Mode0
A=10
A=1
A=4
x
Don’t care
Divider X
B
B
- 56 -
A=10,B=15
A=0,B=11
A=1,B=15
A=2,B=11
A=4,B=15
A=6,B=11
NuMicro™ NUC100 Data Sheet
Mode1
BRD Baud rate equation
A
A
A
UART_CLK / [16 * (A+2)]
UART_CLK / [(B+1) * (A+2)] , B must >= 8
UART_CLK / (A+2), A must >=3
Publication Release Date: Nov. 11, 2010
Mode2
A=190
A=22
A=46
A=94
Revision V2.00