NUMICRO-SDK Nuvoton Technology Corporation of America, NUMICRO-SDK Datasheet - Page 350

• Manufacturer Part Number: NUMICRO-SDK
• Description: KIT EVAUATION NUC100/120/130/140
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r
• Type: MCUr

Specifications of NUMICRO-SDK

• Contents: Board, Cable, CD, Nu-Link
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: NUC100, NUC120, NUC130, NUC140

5.9.5
In master/slave mode, the active level of device/slave select (SPISSx) signal can be programmed
to low active or high active in SS_LVL bit (SPI_SSR[2]), but the SPISSx0/1 is level trigger or edge
trigger which is defined in SS_LTRIG bit (SPI_SSR[4]). The serial clock (SPICLK) idle state can
be configured as high state or low state by setting the CLKP bit (SPI_CNTRL[11]). It also provides
the bit length of a transaction word in TX_BIT_LEN (SPI_CNTRL[7:3]), the transfer number in
TX_NUM (SPI_CNTRL[8]), and transmit/receive data from MSB or LSB first in LSB bit
(SPI_CNTRL[10]). Users also can select which edge of serial clock to transmit/receive data in
TX_NEG/RX_NEG (SPI_CNTRL[2:1]) registers. Four SPI timing diagrams for master/slave
operations and the related settings are shown as below.
SPICLK
SPISS
Timing Diagram
MOSI
MISO
Master Mode: CNTRL[SLVAE]=0, CNTRL[LSB]=0, CNTRL[TX_NUM]=0x0, CNTRL[TX_BIT_LEN]=0x08
NuMicro™ NUC100 Series Technical Reference Manual
SS_LVL=1
SS_LVL=0
CLKP=0
CLKP=1
1. CNTRL[CLKP]=0, CNTRL[TX_NEG]=1, CNTRL[RX_NEG]=0 or
2. CNTRL[CLKP]=1, CNTRL[TX_NEG]=0, CNTRL[RX_NEG]=1
TX0[7]
RX0[7]
MSB
MSB
Figure 5-58 SPI Timing in Master Mode
RX0[6]
TX0[6]
RX0[5]
TX0[5]
- 350 -
RX0[4]
TX0[4]
Publication Release Date: Dec. 22, 2010
RX0[3]
TX0[3]
RX0[2]
TX0[2]
RX0[1]
TX0[1]
Revision V1.06
RX0[0]
TX0[0]
LSB
LSB