DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 9

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 2: Board Components
Featured Device: MAX V CPLD
Table 2–1. MAX V CPLD Development Board Components (Part 2 of 2)
Featured Device: MAX V CPLD
Table 2–2. MAX V CPLD 5M570ZF256C5N Device Features
January 2011 Altera Corporation
U3
U4
J13, J14
D1
D3
Clock Circuitry
J1
X1
Y1
Connectors
J6, J7
J9
J5, J10
General User Input/Output
D7, D8
S1, S2
CPB1
Off-Chip EEPROM
U6
U8
Board Reference
Equivalent LEs
570
f
USB 2.0 PHY
CPLD
JTAG header
Power LED
USB LED
10-MHz oscillator
6-MHz oscillator
24-MHz oscillator
GPIO headers
PC speaker header
DC motor headers
User LEDs
User push-button switches
Capacitor sense button
I
SPI EEPROM
2
C EEPROM
The MAX V CPLD development board features the MAX V CPLD 5M570ZF256C5N
device (U5) in a 256-pin FBGA package.
Table 2–2
For more information about MAX V CPLD device family, refer to the
Handbook.
User Flash Memory (bits)
Type
describes the features of the MAX V CPLD 5M570ZF256C5N device.
8192
A FTDI USB 2.0 PHY device to configure the CPLD over embedded
USB-Blaster.
MAX II CPLD EPM240M100.
Footprint (at the bottom of the board) to mount a JTAG header. The
header allows direct-access to devices in the JTAG connection.
Illuminates when 5-V USB power is present.
Illuminates to indicate USB-JTAG activity.
10-MHz single-ended input clock for the MAX V CPLD.
6-MHz input clock for the FTDI USB 2.0 PHY device.
24-MHz input clock for the MAX II CPLD EPM240M100.
Two general-purpose 2x40-pin 0.1-inch expansion headers.
A 4-pin PC speaker header which connects to the MAX V CPLD I/O
bank 2.
Two motor headers which connects to the MAX V CPLD I/O bank 2.
Two user LEDs. Illuminates when driven low.
Two user push-button switches. Driven low when pressed.
One capacitive touch-sense user-defined button.
Footprint to install an I
Footprint to install a SPI EEPROM.
User I/Os
159
2
C serial EEPROM
MAX V CPLD Development Board Reference Manual
Global Clocks
Description
4
Package Type
256-pin FBGA
MAX V Device
2–3