DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet
DK-DEV-3SL150N
Specifications of DK-DEV-3SL150N
Available stocks
Related parts for DK-DEV-3SL150N
DK-DEV-3SL150N Summary of contents
Page 1
... III family provides one of the most architecturally advanced, high-performance, low-power FPGAs in the marketplace. Stratix III FPGAs lower power consumption through Altera’s innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption for blocks not in use. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industry’ ...
Page 2
... M144K TriMatrix memory blocks ■ Nios II embedded processor support ® ■ Support for multiple intellectual property megafunctions from Altera functions and Altera Megafunction Partners Program (AMPP Stratix III Device Handbook, Volume 1 Chapter 1: Stratix III Device Family Overview Features Summary MegaCore ® ...
Page 3
... Stratix III devices are available in space-saving FineLine BGA (FBGA) packages (refer to Table 1–2 and © March 2010 Altera Corporation Total M9K M144K MLAB Embedded Blocks ...
Page 4
... FineLine BGA FineLine BGA (3) (3) — — — — — — — — 976 — 976 1,120 — — — — — — 976 — II ® 1517 Pin 1760 Pin 1.00 1.00 1,600 1,849 40/40 43/43 © March 2010 Altera Corporation ...
Page 5
... Commercial –4L EP3SE50 Industrial –3, –4, –4L Commercial — EP3SE80 Industrial — Commercial — EP3SE110 Industrial — © March 2010 Altera Corporation Dimension 780-Pin 780-Pin 1152-Pin Hybrid FineLine FineLine FineLine BGA BGA BGA –2, –3,–4, — — –4L – ...
Page 6
... Chapter 1: Stratix III Device Family Overview Architecture Features 1152-Pin 1517-Pin 1760-Pin Hybrid FineLine FineLine FineLine BGA BGA BGA –2, –3, –4, — — –4L — –3, –4,–4L — Logic Array Blocks and chapter. © March 2010 Altera Corporation ...
Page 7
... DSP blocks to implement finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, and discrete cosine transform (DCT) functions. © March 2010 Altera Corporation MultiTrack Interconnect in Stratix III Devices TriMatrix Embedded Memory Blocks in Stratix III Devices Stratix III Device Handbook, Volume 1 1– ...
Page 8
... Stratix III PLLs also support external feedback mode, spread-spectrum input clock tracking, and post-scale counter cascading. Stratix III Device Handbook, Volume 1 Chapter 1: Stratix III Device Family Overview DSP Blocks in Stratix III Devices chapter. © March 2010 Altera Corporation Architecture Features ...
Page 9
... SFI-4, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI. Stratix III devices support 2×, 4×, 6×, 7×, 8×, and 10× SERDES modes for high-speed differential I/O interfaces and © March 2010 Altera Corporation Clock Networks and PLLs in Stratix III Devices ) termination with auto calibration for single-ended I/O standards ...
Page 10
... All configuration schemes use either an external controller (for example, a MAX device or microprocessor), a configuration device download cable. Stratix III Device Handbook, Volume 1 High Speed Differential I/O Interfaces with DPA in chapter. Hot Socketing and Power-On Reset in Stratix III Chapter 1: Stratix III Device Family Overview Architecture Features II ® © March 2010 Altera Corporation ...
Page 11
... Advanced Encryption Standard (AES) algorithm, an industry standard encryption algorithm that is FIPS-197 certified and requires a 256-bit security key. © March 2010 Altera Corporation Configuring Stratix III Devices Remote System Upgrades with Stratix III Devices IEEE 1149.1 (JTAG) Boundary Scan Testing in chapter. 1– ...
Page 12
... Programmable Power and Temperature Sensing Diode in Stratix III Devices ■ AN 437: Power Optimization in Stratix III FPGAs ■ ■ Stratix III Programmable Power White Paper Stratix III Device Handbook, Volume 1 chapter. chapter. Chapter 1: Stratix III Device Family Overview Architecture Features Design Security in SEU chapter © March 2010 Altera Corporation ...
Page 13
... The following section describes Stratix III device software support and ordering information. Software Support Stratix III devices are supported by the Altera Quartus II design software, version 6.1 and later, which provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and ...
Page 14
... Chapter 1: Stratix III Device Family Overview Chapter Revision History Stratix III Device Package Optional Suffix Indicates specific device options ES: Engineering sample N: Lead-free devices L: Low-voltage devices Speed Grade with 2 being the fastest Operating Temperature C: Commercial temperature ( Industrial temperature ( 100 C) J © March 2010 Altera Corporation ...
Page 15
... Minor formatting changes, fixed PLL numbers and ALM, LE and MLAB bit counts in May 2007 1.1 Table 1–1. November 2006 1.0 Initial Release. © March 2010 Altera Corporation Changes Made Updated “Introduction”. Updated Table 1–1. Updated Table 1–2. Added Table 1–5. Updated “Reference and Ordering Information”. ...
Page 16
... Stratix III Device Handbook, Volume 1 Chapter 1: Stratix III Device Family Overview Chapter Revision History © March 2010 Altera Corporation ...