AGLN250V2-VQG100 Actel, AGLN250V2-VQG100 Datasheet - Page 56

• Manufacturer Part Number: AGLN250V2-VQG100
• Description: FPGA - Field Programmable Gate Array 250K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN250V2-VQG100

• Processor Series: AGLN250
• Core: IP Core
• Number Of Macrocells: 2048
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 68
• Data Ram Size: 36 Kbit
• Supply Voltage (max): 1.5 V
• Supply Current: 34 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 250 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO nano DC and Switching Characteristics
Table 2-70 • Parameter Definition and Measuring Nodes
2- 42
Parameter Name
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*
OCLKQ
OSUD
OHD
OPRE2Q
OREMPRE
ORECPRE
OECLKQ
OESUD
OEHD
OEPRE2Q
OEREMPRE
OERECPRE
ICLKQ
ISUD
IHD
IPRE2Q
IREMPRE
IRECPRE
See
Figure 2-12 on page 2-41
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
for more information.
Parameter Definition
R ev i sio n 1 1
Measuring Nodes
(from, to)*
H, DOUT
H, EOUT
L, DOUT
I, EOUT
C, A
C, A
D, E
D, A
F, H
L, H
L, H
J, H
A, E
D, A
F, H
J, H
I, H
I, H