DC1298A-LA Linear Technology, DC1298A-LA Datasheet - Page 24

• Manufacturer Part Number: DC1298A-LA
• Description: BOARD EVAL LTM9002-LA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1298A-LA

• Design Resources: Demo Circuit 1298A Schematic
• Frequency: 0Hz ~ 300MHz
• Features: LTM9002 14bit Dual Receiver Subsystem, DC-25MHz LPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9002
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9002
• Lead Free Status / RoHS Status: Not applicable / Not applicable

LTM9002
APPLICATIONS INFORMATION
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non 50% duty
cycle. Using the clock duty cycle stabilizer is recommended
for most applications. To use the clock duty cycle stabilizer,
the MODE pin should be connected to 1/3V
using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40% to
60% and the clock duty cycle stabilizer will maintain a
constant 50% internal duty cycle. If the clock is turned off
for a long period of time, the duty cycle stabilizer circuit
will require a hundred clock cycles for the PLL to lock
onto the input clock.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle.
DIGITAL OUTPUTS
Table 6 shows the relationship between the analog input
voltage, the digital data bits, and the overfl ow bit. Note that
OF is high when an overfl ow or underfl ow has occurred
on either channel A or channel B.
Table 6. Output Codes vs Input Voltage, 100mV Input Span
24
(SENSE = V
0.000000V
≤ –50mV
IN
≥ 50mV
+
– IN
–
DD
)
OF
1
0
0
0
0
0
0
0
0
1
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
(OFFSET BINARY)
D13 - D0
(2’S COMPLEMENT)
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
DD
D13 - D0
or 2/3V
DD
Digital Output Modes
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by O
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
As with all high speed/high resolution converters the digital
output loading can affect the performance. The digital
outputs of the ADC should drive a minimal capacitive load
to avoid possible interaction between the digital outputs
and sensitive input circuitry. For full-speed operation, the
capacitive load should be kept under 10pF .
Lower OV
from the digital outputs.
LATCH
FROM
DATA
OE
PREDRIVER
DD
LOGIC
V
DD
voltages will also help reduce interference
Figure 12. Digital Output Buffer
V
DD
VDD
and OGND, isolated
OV
DD
LTM9002
43Ω
0.1μF
9002 F12
OV
OGND
DD
0.5V
TO 3.6V
TYPICAL
DATA
OUTPUT
9002f