DC1437B-AA Linear Technology, DC1437B-AA Datasheet - Page 18

• Manufacturer Part Number: DC1437B-AA
• Description: BOARD EVAL LTM9003-AA
• Manufacturer: Linear Technology
• Type: Pre-Distortion Receiver Subsystemr

Specifications of DC1437B-AA

• Design Resources: DC1437 Schematic
• Frequency: 184MHz
• Features: LTM9003 12bit Predistortion Receiver Subsystem
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9003
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9003
• Lead Free Status / RoHS Status: Not applicable / Not applicable

LTM9003
applicaTions inForMaTion
CLOCK
Maximum and Minimum Conversion Rates
The maximum conversion rate for the ADC is 250Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 1.9ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS.

INPUT
Figure 9. Single-Ended ENC Driver, Not Recommended
for Low Jitter
0.1µF
0.1µF
V
•
ETC1-1-13
THRESHOLD
Figure 8. Transformer Driven ENC
MA/COM
T1
Figure 10. ENC Drive Using LVDS
CLOCK
LVDS
•
= 1.5V
8.2pF
ENC –
ENC
+
0.1µF
0.1µF
0.1µF
LTM9003
100
1.5V
ENC
ENC
+
–
V
V
ENC
ENC
DD
DD
LTM9003
+
–
1.5V
BIAS
1.5V
BIAS
4.8k
4.8k
LTM9003
9003 F10
+
V
/ENC
DD
9003 F09
–
ADC CIRCUITS
TO INTERNAL
9003 F08
The lower limit of the sample rate is determined by the
droop of the sample-and-hold circuits. The pipelined ar-
chitecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTM9003 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit can be used if
the input clock has a non 50% duty cycle. This circuit uses
the rising edge of the ENC
The falling edge of ENC
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 40% to 60% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3V
Clock Sources for Undersampling
Undersampling is especially demanding on the clock source
and the higher the input frequency, the greater the sensitivity
to clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required, a
canned oscillator from vendors such as Saronix or Vectron
can be placed close to the ADC and simply connected
directly to the ADC. If there is any distance to the ADC,
some source termination to reduce ringing that may occur
even over a fraction of an inch is advisable. You must not
allow the clock to overshoot the supplies or performance
will suffer. Do not filter the clock signal with a narrow band
filter unless you have a sinusoidal clock source, as the
rise and fall time artifacts present in typical digital clock
signals will be translated into phase noise.
DD
or 2/3V
+
is ignored and the internal falling
+
pin to sample the analog input.
DD
using external resistors.
9003f