DC1437B-AA Linear Technology, DC1437B-AA Datasheet - Page 19

• Manufacturer Part Number: DC1437B-AA
• Description: BOARD EVAL LTM9003-AA
• Manufacturer: Linear Technology
• Type: Pre-Distortion Receiver Subsystemr

Specifications of DC1437B-AA

• Design Resources: DC1437 Schematic
• Frequency: 184MHz
• Features: LTM9003 12bit Predistortion Receiver Subsystem
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9003
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9003
• Lead Free Status / RoHS Status: Not applicable / Not applicable

applicaTions inForMaTion
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
the filter and the ADC. If the circuit is sensitive to close-
in phase noise, the power supply for oscillators and any
buffers must be very stable, or propagation delay variation
with supply will translate into phase noise. Even though
these clock sources may be regarded as digital devices, do
not operate them on a digital supply. If your clock is also
used to drive digital devices such as an FPGA, you should
locate the oscillator, and any clock fan-out devices close to
the ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination at
the driver to prevent high frequency noise from the FPGA
disturbing the substrate of the clock fan-out device. If you
use an FPGA as a programmable divider, you must re-time
the signal using the original oscillator, and the re-timing
flip-flop as well as the oscillator should be close to the
ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated in
the waveguides that exist between the layers of multilayer
PCBs. The differential pairs must be close together and
distanced from other signals. The differential pair should
be guarded on both sides with copper distanced at least
3x the distance between the traces, and grounded with
vias no more than 1/4 inch apart.
Digital Outputs
Table 3 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Table 3. Output Codes vs Input Voltage
Overvoltage
Maximum
0.000000V
Minimum
Undervoltage
Digital Output Buffers
Figure 11 shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT+ to OUT– or vice versa which creates a
±350mV differential voltage across the 100Ω termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100Ω
LTM9003
(SENSE = V
INPUT
–
+
DD
D
D
Figure 11. Digital Output in LVDS Mode
1.25V
)
OF
1
0
0
0
0
0
0
0
0
1
10k
(OFFSET BINARY)
1111 1111 1111
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
10k
D11 – D0
3.5mA
OV
DD
D
D
0.1µF
9003 F11
LTM9003
(2’S COMPLEMENT)
OUT
OUT
100
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
+
–
OGND
D11 – D0
2.5V
RECEIVER

LVDS
9003f