DC1298A-AA Linear Technology, DC1298A-AA Datasheet - Page 17

• Manufacturer Part Number: DC1298A-AA
• Description: BOARD EVAL LTM9002-AA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1298A-AA

• Design Resources: Demo Circuit 1298A Schematic
• Frequency: 0Hz ~ 300MHz
• Features: LTM9002 14bit Dual Receiver Subsystem, DC-170MHz LPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9002
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9002
• Lead Free Status / RoHS Status: Not applicable / Not applicable

OPERATION
Note that not all combinations in Table 1 are possible at
this time and specifi ed performance may differ signifi cantly
from existing values.
AMPLIFIER OPERATION
The amplifi ers used in the LTM9002 are low noise and
low distortion fully differential op amps/ADC drivers with
operation from DC to 2GHz (–3dB bandwidth). The ampli-
fi ers are composed of fully differential amplifi ers with on
chip feedback and output common mode voltage control
circuitry. Differential gain and input impedance are set by
internal resistors in the feedback network.
Table 2. Amplifi er Gain and Input Impedance
The amplifi ers are very fl exible in terms of I/O coupling.
They can be AC- or DC-coupled at the inputs. Due to the
internal connection between input and output, users are
advised to keep input common mode voltage between 1V
and 1.7V for proper operation. If the inputs are AC-coupled,
the input common mode voltage is automatically biased
close to the ADC input common mode voltage and thus no
external circuitry is needed for bias. The input signal can
be either single-ended or differential with some difference
in distortion performance.
ADC INPUT NETWORK
The passive network between the amplifi er output stage
and the ADC input stage provides a 3rd order topology
that can be confi gured for bandpass or lowpass response
and different cutoff frequencies and bandwidths. LTM9002-
AA, for example, implements a lowpass fi lter designed
for 170MHz.
CONVERTER OPERATION
As shown in the Block Diagram, the analog-to-digital con-
verter (ADC) is a dual CMOS pipelined multistep converter.
The converter has six pipelined ADC stages; a sampled
GAIN (dB)
14
20
26
8
GAIN (V/V)
2.5
10
20
5
Z
IN
(DIFFERENTIAL)
400Ω
200Ω
200Ω
50Ω
analog input will result in a digitized value six cycles
later (see the Timing Diagram section). The CLK inputs
are single-ended. The ADC has two phases of operation,
determined by the state of the CLK input pins.
Each pipelined stage shown in the Block Diagram contains
an ADC, a reconstruction DAC and an interstage residue
amplifi er. In operation, the ADC quantizes the input to
the stage and the quantized value is subtracted from the
input by the DAC to produce a residue. The residue is
amplifi ed and output by the residue amplifi er. Successive
stages operate out of phase so that when the odd stages
are outputting their residue, the even stages are acquiring
that residue and visa versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the Block Diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifi er which drives the fi rst pipelined ADC
stage. The fi rst stage acquires the output of the S/H dur-
ing this high phase of CLK. When CLK goes back low, the
fi rst stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back to
acquiring the analog input. When CLK goes back high, the
second stage produces its residue which is acquired by the
third stage. An identical process is repeated for the third,
fourth and fi fth stages, resulting in a fi fth stage residue
that is sent to the sixth stage ADC for fi nal evaluation.
Each ADC stage following the fi rst has additional range to
accommodate fl ash and amplifi er offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
AUXILIARY DAC OPERATION
The full-scale voltage span of each ADC is controlled by an
auxiliary voltage output DAC connected to SENSE. Series
resistance in the DAC output allows an external voltage
to override the DAC.
The internal reference sets both auxiliary DACs to a full-
scale range to 1.5V. Programming the DAC to generate
an internal voltage greater than or less than the external
LTM9002
17
9002f