DC1298A-AA Linear Technology, DC1298A-AA Datasheet - Page 22

• Manufacturer Part Number: DC1298A-AA
• Description: BOARD EVAL LTM9002-AA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1298A-AA

• Design Resources: Demo Circuit 1298A Schematic
• Frequency: 0Hz ~ 300MHz
• Features: LTM9002 14bit Dual Receiver Subsystem, DC-170MHz LPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9002
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9002
• Lead Free Status / RoHS Status: Not applicable / Not applicable

LTM9002
APPLICATIONS INFORMATION
exceed ±50mV. The internal 1000pF capacitor provides a
corner frequency of 64kHz when used with the 2.5k ex-
ternal resistor. An additional 0.1μF bypass capacitor may
be required at the SENSE pin.
The auxiliary DACs can be used without an external ref-
erence in applications that are not sensitive to close-in
phase noise such as CCD imaging or oversampling of low
amplitude signals. Without an external reference, the DAC
step size will be 366μV at the SENSE pin which results in
a 18μV step for the input span. In this case, the SENSE
pin may be bypassed with 0.1μF capacitor.
The auxiliary DACs must be subsequently set each time
the LTM9002 is powered up.
22
1V (OPEN CIRCUIT,
RESISTANCE)
4k THEVENIN
REF
1.25V
2.5k
10k
SENSE
SINUSOIDAL
Figure 9. Sinusoidal Single-Ended CLK Driver
CLOCK
INPUT
Figure 8. Using an External Reference
10k
1000pF
50Ω
4.7μF
SELECT
0.1μF
RANGE
1k
1k
DAC
NC7SVU04
Driving the Clock Inputs
The CLK inputs can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with a
low-jitter squaring circuit before the CLK pin (Figure 9).
The noise performance of the ADC can depend on the clock
signal quality as much as on the analog input. Any noise
present on the CLK signal will result in additional aperture
jitter that will be RMS summed with the inherent ADC
aperture jitter. In applications where jitter is critical, such
as when digitizing high input frequencies, use as large an
amplitude as possible. Also, if the ADC is clocked with a
sinusoidal signal, fi lter the CLK signal to reduce wideband
noise and distortion products generated by the source.
FERRITE
BEAD
0.1μF
CLK
REFERENCE
BUFFER
REF
1.5V
SUPPLY
CLEAN
LTM9002
LTM9002
9002 F08
9002 F09
SDI
SCK
CS/LD
9002f