LIS3L02DQ STMicroelectronics, LIS3L02DQ Datasheet - Page 8

• Manufacturer Part Number: LIS3L02DQ
• Description: ACCELEROMETER TRPL AXIS 44QFN
• Manufacturer: STMicroelectronics

Specifications of LIS3L02DQ

• Axis: X, Y, Z
• Acceleration Range: ±2g
• Sensitivity: 1024 LSb/g
• Voltage - Supply: 2.7 V ~ 3.6 V
• Output Type: Digital
• Bandwidth: 1.5kHz
• Interface: I²C, SPI
• Mounting Type: Surface Mount
• Package / Case: 44-QFN
• Sensing Axis: X, Y, Z
• Acceleration: 2 g
• Digital Output - Number Of Bits: 12 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Digital Output - Bus Interface: I2C, SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4129; LIS3L02DQ; Q2094276

LIS3L02DQ
6
The registers embedded inside the LIS3L02DQ may be accessed through both the I
terfaces. The latter may be software configured to operate either in SPI mode or in 3-wire interface mode.
The serial interfaces are mapped onto the same pads. To select the I
high (i.e connected to Vdd).
Table 6. Serial Interface Pin Description
6.1 I
The LIS3L02DQ I
the registers whose content can also be read back.
The relevant I
Table 7. Serial Interface Pin Description
There are two signals associated with the I
(SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both
the lines are connected to Vdd through a pull-up resistor embedded inside the LIS3L02DQ. When the bus
is free both lines are high.
The I
6.2 I
The transaction on the bus is started through a START signal. A START condition is defined as a HIGH
to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the
Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the
address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the
slave or transmitting data to the slave. When an address is sent, each device in the system compares the
first seven bits after a start condition with its address. If they match, the device considers itself addressed
by the Master.The Slave ADdress (SAD) associated to the LIS3L02DQ is 0011101.
It’s mandatory to use “acknowledge” during data transfer. The transmitter must release the SDA line dur-
8/20
CS
SCL/SPC
SDA/SDI/SDO
SDO
Transmitter
Receiver
Master
Slave
Digital Interfaces
2
2
2
PIN Name
C interface is compliant with Fast Mode (400 kHz) I
C Serial Interface
C Operation
Term
2
C terminology is given in the table below:
2
C is a bus slave. The I
SPI enable
I
I
SPI Serial Port Clock (SPC)
I
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
The device which sends data to the bus
The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
2
2
2
C/SPI mode selection (1: I
C Serial Clock (SCL)
C Serial Data (SDA)
2
C is implemented in the way that the data can be written into
2
C bus: the Serial Clock Line (SCL) and the Serial Data line
2
C mode; 0: SPI enabled)
PIN Description
Description
2
C standards as well as the Normal Mode.
2
C interface, CS line must be tied
2
C and SPI serial in-