78Q8430-100CGT/F TERIDIAN, 78Q8430-100CGT/F Datasheet - Page 3

• Manufacturer Part Number: 78Q8430-100CGT/F
• Description: IC, ETHERNET TXRX, IEEE 802.3, LQFP-100
• Manufacturer: TERIDIAN

Specifications of 78Q8430-100CGT/F

• No. Of Ports: 2
• Ethernet Type: IEEE 802.3x, IEEE 802.3u, IEEE 802.3-2000
• Ic Interface Type: Host Bus, JTAG
• Supply Voltage Range: 0V To 3.3V
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In 10BASE-T mode, the 20MHz receive clock is
recovered digitally from the Manchester data using a
DLL locked to the reference clock.
Manchester-coded preambles are detected, the
CDR immediately re-aligns the phase of the clock to
synchronize with the incoming data. Hence clock
acquisition is fast and immediate.
100BASE-TX OPERATION
100BASE-TX Transmit
The 78Q2123/78Q2133 contain all of the necessary
circuitry to convert the transmit MII signaling from a
MAC to an IEEE-802.3 compliant data-stream
driving Cat-5 UTP cabling.
interface maps 4 bit nibbles from the MII to 5 bit
code groups as defined in Table 24-1 of IEEE-802.3.
These 5 bit code groups are then scrambled and
converted to a serial stream before being sent to the
MLT-3 pulse shaping circuitry and line driver. The
pulse-shaper uses current modulation to produce the
desired output waveform. Controlled rise/fall time in
the MLT-3 signal is achieved using an accurately
controlled voltage ramp generator. The line driver
requires an external 1:1 isolation transformer to
interface with the line media. The center-tap of the
primary side of the transformer must be connected
to the Vcc supply (3.3V ± 0.3V).
100BASE-TX Receive
The 78Q2123/78Q2133 receive a 125MBaud MLT-3
signal through a 1:1 transformer. The signal then
goes through a combination of adaptive offset
adjustment
adaptive equalization. The effect of these circuits is
to sense the amount of dispersion and attenuation
caused by the cable and transformer, and restore
the received pulses to logic levels. The amount of
gain and equalization applied to the pulses varies
with the detected attenuation and dispersion and,
therefore, with the length of the cable.
78Q2123/78Q2133 can compensate for cable loss
of up to 10dB at 16 MHz. This loss is represented
as test-chan 5 in Annex A of the ANSI X3.263:199X.
The equalized MLT-3 data signal is bi-directionally
sliced and the resulting NRZI bit-stream is presented
to the CDR where it is re-timed and decoded to NRZ
format. The re-timed serial data passes through a
serial-to-parallel converter, then descrambled and
aligned into 5 bit code groups. The receive PCS
interface maps these code groups to 4 bit data for
the MII as outlined in Table 24-1 in Clause 24 of
IEEE-802.3.
Page: 3 of 39
(baseline
wander
The internal PCS
correction)
©
2006 Teridian Semiconductor Corporation
When
The
and
PCS Bypass Mode (Auto-negotiate must be off)
The PCS Bypass mode is entered by setting register
bit MR 16.1. In this mode the 78Q2123/78Q2133
accept scrambled 5 bit code words at the TX_ER
and TXD[3:0] pins, TX_ER being the MSB of the
data input. The 5 bit code groups are converted to
MLT-3 signal for transmission.
The received MLT-3 signal is converted to 5 bit NRZ
code groups and output from the RX_ER and
RXD[3:0] pins, RX_ER being the MSB of the data
output. The RX_DV and TX_EN pins are unused in
PCS Bypass mode.
10BASE-T OPERATION
10BASE-T Transmit
The 78Q2123/78Q2133 take 4-bit parallel NRZ data
via the MII interface and passes it through a parallel
to serial converter. The data is then passed through
a Manchester encoder, pre-emphasis pulse-shaper,
media filter, and finally to the twisted-pair line driver.
The pulse-shaper and filter ensure the output
waveforms meet the voltage template and spectral
content requirements detailed in Clause 14 of IEEE-
802.3. Interface to the twisted-pair media is through
a center-tapped 1:1 transformer.
filtering is required.
10BASE-T idle periods, link pulses are transmitted.
The 78Q2123/78Q2133 employ an onboard timer to
prevent the MAC from capturing a network through
excessively long transmissions.
expires, the chip enters the jabber state and
transmission is halted. The jabber state is exited
after the MII goes idle for 500±250ms.
10BASE-T Receive
The
encoded 10BASE-T data through the twisted pair
inputs and re-establishes logic levels through a slicer
with a smart squelch function.
automatically adjusts its level after detection of valid
data with the appropriate levels. Data is passed on
to the CDR where the clock is recovered, and the
data is re-timed and decoded.
enters
transmission to the MAC via the Media Independent
Interface.
through an external 1:1 transformer.
information is detected and corrected within internal
circuitry.
78Q2123/78Q2133
the
78Q2123/78Q2133 MicroPHY™
Interface to the twisted-pair media is
10/100BASE-TX Transceiver
serial-to-parallel
During auto-negotiation and
receive
From there, data
When this timer
converter
No external
Manchester-
The slicer
Polarity
Rev 1.1
for