DP83815DUJB National Semiconductor, DP83815DUJB Datasheet - Page 51
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DP83815DUJB
Manufacturer Part Number
DP83815DUJB
Description
IC, ENET CTRL 10BASET, 100MBPS, LBGA-160
Manufacturer
National Semiconductor
Datasheet
1.DP83815DUJB.pdf
(108 pages)
Specifications of DP83815DUJB
Data Rate
100Mbps
Ethernet Type
10BASE-T
Supply Current
170mA
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
0°C To +70°C
No. Of Pins
160
Termination Type
SMD
Filter Terminals
SMD
Rohs Compliant
No
Data Rate Max
100Mbps
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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4.0 Register Set
4.2.11 Receive Descriptor Pointer Register
This register points to the current Receive Descriptor.
22-20
19-14
13-8
31-2
Bit
Bit
7-6
5-0
1-0
Bit Name
Bit Name
MXDMA
DRTH
RXDP
FLTH
Offset: 0030h
(Continued)
Tag: RXDP
Max DMA Burst Size per Tx DMA Burst
This field sets the maximum size of transmit DMA data bursts according to the following table:
NOTE: The MXDMA setting value MUST not be greater than the TXCFG:FLTH (Tx Fill Threshold) value.
unused
Tx Fill Threshold
Specifies the fill threshold in units of 32 bytes. When the number of available bytes in the transmit FIFO
reaches this level, the transmit bus master state machine will be allowed to request the PCI bus for
transmit packet fragment reads. A value of 0 in this field will produce unexpected results and must not be
used.
Note: The FLTH value should be greater than the TXCFG:MXDMA value, but less than (txFIFOsize -
TXCFG:DRTH). In order to prevent FIFO pointer overlap internal to the device, the sum of the FLTH and
TXCFG:DRTH values should not exceed 2016 Bytes.
unused
Tx Drain Threshold
Specifies the drain threshold in units of 32 bytes. When the number of bytes in the FIFO reaches this
level (or the FIFO contains at least one complete packet) the MAC transmit state machine will begin the
transmission of a packet.
NOTE: In order to prevent a deadlock condition from occurring, the DRTH value should always be less
than (txFIFOsize - TXCFG:FLTH). A value of 0 in this field will produce unexpected results and must not
be used. Also, in order to prevent FIFO pointer overlap internal to the device, the sum of the DRTH and
TXCFG:FLTH values should not exceed 2016 Bytes.
Receive Descriptor Pointer
The current value of the receive descriptor pointer. When the receive state machine is idle, software must
set RXDP to the address of an available receive descriptor. While the receive state machine is active,
RXDP will follow the state machine as it advances through a linked list of available descriptors. If the link
field of the current receive descriptor is NULL (signifying the end of the list), RXDP will not advance, but
will remain on the current descriptor. Any subsequent writes to the RXE bit of the CR register will cause
the receive state machine to reread the link field of the current descriptor to check for new descriptors
that may have been appended to the end of the list. Software should not write to this register unless the
receive state machine is idle. Receive descriptors must be aligned on 32-bit boundaries (A1-A0 must be
zero). A 0 written to RXDP followed by a subsequent write to RXE will cause the receiver to enter silent
RX mode, for use during WOL. In this mode packets will be received and buffered in FIFO, but no DMA
to system memory will occur. The packet data may be recovered from the FIFO by writing a valid
descriptor address to RXDP and then strobing RXE.
unused
000 = 128 32-bit words (512 bytes)
001 = 1 32-bit word (4 bytes)
010 = 2 32-bit words (8 bytes)
011 = 4 32-bit words (16 bytes)
100 = 8 32-bit words (32 bytes)
101 = 16 32-bit words (64 bytes)
110 = 32 32-bit words (128 bytes)
111 = 64 32-bit words (256 bytes)
Access: Read Write
Size: 32 bits
51
Description
Description
Hard Reset: 00000000h
Soft Reset: 00000000h
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