VNC2-48L1B FTDI, VNC2-48L1B Datasheet
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VNC2-48L1B
Specifications of VNC2-48L1B
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VNC2-48L1B Summary of contents
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... The designers also have the ability to create their own firmware using the new suite of software development tools. VNC2 has the following advanced features: Embedded processor core. 16 bit Harvard architecture. ...
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... Data logging similar USB slave device interface e.g. USB external drive. 1.1 Application, Technical Notes and Toolchain download links The following VNC2 documents and the full Toolchain software suite can be downloaded by clicking on the appropriate links below: Technical note TN_108 Technical note TN_118 ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 1.2 Part Numbers Part Numbers Part Number VNC2-64L1B VNC2-64Q1B VNC2-48L1B VNC2-48Q1B VNC2-32L1B VNC2-32Q1B Table 1 Part Numbers Please refer to section 11 for all package mechanical parameters. 1.3 USB Compliant At time of writing this data sheet, VNC2 has not completed USB compliancy testing. ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 1.4 Acronyms and Abbreviations Terms USB FIFO SPI PWM GPIO I/O VNC1L VNC2 DMA IDE BOMS UART SIE CPU SoC FAT RTOS VOS OSI MOSI MISO SE0 EMCU FPGA Table 2 Acronyms and Abbreviations Copyright © 2010 Future Technology Devices International Limited ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 2 VNC2 Block Diagram Figure 2-1 Simplified VNC2 Block Diagram For a description of each function please refer to UART PWMs FIFO Interface SPI Master SPI Slave 1 SPI Slave 0 GPIOS General Purpose Timers Debugger I/F USB Host/ USB1DP ...
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... Pin Out - 64 pin LQFP ....................................................................... 13 3.6 Pin Out - 64 pin QFN ........................................................................ 14 3.7 VNC2 Schematic symbol 32 Pin ......................................................... 15 3.8 VNC2 Schematic symbol 48 Pin ......................................................... 16 3.9 VNC2 Schematic symbol 64 Pin ......................................................... 17 3.10 Pin Configuration USB and Power .................................................. 18 3.11 Miscellaneous Signal ...................................................................... 19 3.12 Pin Configuration Input / Output ................................................... 20 4 Function Description................................................................... 23 4 ...
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... RTOS ................................................................................................. 69 8.2 Device drivers ................................................................................... 69 8.3 Firmware – Software Deveolment Tool Chain ................................... 70 8.4 Precompiled Firmware ...................................................................... 71 9 Device Characteristics and Ratings ............................................. 72 9.1 Absolute Maximum Ratings............................................................... 72 9.2 DC Characteristics............................................................................. 73 Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 7 ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 9.3 ESD and Latch-up Specifications ....................................................... 75 10 Application Examples ................................................................. 76 10.1 Example VNC2 Schematic (MCU – UART Interface) ........................ 76 11 Package Parameters ................................................................... 77 11.1 VNC2 Package Markings ................................................................ 77 11.2 VNC2, LQFP-32 Package Dimensions .............................................. 78 11.3 VNC2, QFN-32 Package Dimensions ............................................... 79 11.4 VNC2, LQFP-48 Package Dimensions ...
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... Device Pin Out and Signal Description Summary VNC2 is available in six packages: 32 pin LQFP, 32 pin QFN, 48 pin LQFP (pin compatible with VNC1L), 48 pin QFN, 64 pin LQFP and 64 pin QFN. Figure 3.3 shows how the VNC2 pins map to the VNC1L pins (VNC2 pins labelled in bold text): 3 ...
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... GND Core 27 XXXXXXXXXX VCCIO 3. BUS8 BUS9 IO BUS10 31 IO BUS11 32 Figure 3-2 32 Pin QFN – Top Down View Copyright © 2010 Future Technology Devices International Limited FTDI VNC2-32Q 1A YYWW Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# GND BUS3 IO BUS2 14 13 VCCIO 3.3V IO BUS1 ...
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... IO BUS25 ACBUS5 46 IO BUS26 ACBUS6 47 IO BUS27 ACBUS7 48 ITALIC TEXT = VNC1 BOLD TEXT = VNC2 Figure 3-3 48 Pin LQFP – Top Down View Copyright © 2010 Future Technology Devices International Limited FTDI XXXXXXXXXX VNC2-48L1A YYWW Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# ...
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... IOBUS21 42 IOBUS22 43 IOBUS23 44 IOBUS24 45 IOBUS25 46 IOBUS26 47 IOBUS27 48 – Top Down View Figure 3-4 48 Pin QFN Copyright © 2010 Future Technology Devices International Limited FTDI VNC2-48Q1A YYWW Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# GND IO 24 IOBUS11 23 22 IOBUS10 IOBUS9 21 IOBUS8 20 IOBUS7 ...
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... IO BUS39 61 IO BUS40 62 IO BUS41 63 IO BUS42 64 IO BUS43 Figure 3-5 64 Pin LQFP – Top Down View Copyright © 2010 Future Technology Devices International Limited FTDI XXXXXXXXXX VNC2-64L1A YYWW Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI BUS19 31 IO BUS18 30 GND IO 29 ...
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... Pin Out - 64 pin QFN IOBUS30 49 IOBUS31 50 IOBUS32 51 IOBUS33 52 GND CORE 53 VCCIO 3.3V 54 IOBUS34 55 XXXXXXXXXX IOBUS35 56 IOBUS36 57 VNC2-64Q1A IOBUS37 58 IOBUS38 59 IOBUS39 60 IOBUS40 61 IOBUS41 62 IOBUS42 63 IOBUS43 64 – Top Down View Figure 3-6 64 Pin QFN Copyright © 2010 Future Technology Devices International Limited FTDI YYWW Document No ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 3.7 VNC2 Schematic symbol 32 Pin Copyright © 2010 Future Technology Devices International Limited USB1DP I N USB1DM USB2DP USB2DM XTIN VNC2 32 Pin XTOUT RESET# PROG# VREG OUT TEST Figure 3-7 Schematic symbol 32 Pin Document No.: FT_000138 Version - Clearance No ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 3.8 VNC2 Schematic symbol 48 Pin Copyright © 2010 Future Technology Devices International Limited USB1DP I N USB1DM USB2DP USB2DM XTIN XTOUT VNC2 48 Pin RESET# PROG# VREG OUT TEST Figure 3-8 Schematic symbol 48 Pin Document No.: FT_000138 Version - Clearance No ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 3.9 VNC2 Schematic symbol 64 Pin 10 Copyright © 2010 Future Technology Devices International Limited USB1DP USB1DM 36 USB2DP 37 USB2DM IOBUS10 4 XTIN IOBUS11 IOBUS12 5 XTOUT IOBUS13 IOBUS14 IOBUS15 9 RESET# IOBUS16 IOBUS17 PROG# IOBUS18 VNC2 IOBUS19 64 Pin IOBUS20 ...
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... Device analogue ground supply for internal clock PWR 1.8V output from regulator to device core Output +3.3V supply to the input / output. Interface pins PWR (IOBUS). Leaving the VCCIO unconnected will lead to unpredictable operation on the interface pins. Document No.: FT_000138 Version - Clearance No.: FTDI# Description Description multiplier. N pin package. 1.2 143 * 18 ...
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... Output from 12MHz Oscillator Cell. Connect 12MHz Output crystal across pins 4 and 5. Input Test Input. Must be tied to GND for normal operation. Input Can be used by an external device to reset VNC2. Asserting PROG# on its own enables programming Input Document No.: FT_000138 1.2 Version - 143 Clearance No ...
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... SPI master, GPIO and PWM. The Interface I/O Multiplexer is used to share the available I/O Pins between each peripheral. VNC2 is configured with default settings for the I/O pins however they can be easily changed to suit the needs of a designer. This is explained in Section 5 – I/O Multiplexer. Default configuration for each package type is shown in Table 6- Default I/O Configuration ...
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... Input Input Input spi_s0_clk spi_s0_mosi spi_s0_miso spi_s0_ss# spi_s1_clk Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 32 PIN Type Description Default I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O ...
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... Copyright © 2010 Future Technology Devices International Limited 64 Pin 48 Pin Default Default spi_s1_mosi spi_s1_miso spi_s1_ss# spi_m_clk spi_m_mosi spi_m_miso spi_m_ss_0# Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 32 PIN Type Description Default I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O ...
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... VNC2 is a programmable SoC device with a powerful embedded microprocessor core and dual USB interfaces, large RAM and Flash capacity and the ability to develop and customise firmware using the VNC2 tool chain. VNC2 has an enhanced feature list over and above VNC1L, however the 48 pin LQFP package is backward compatible with the VNC1L. ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 4.2.4 Input / Output Multiplexer Module VNC2 peripheral interfaces are UART, SPI slave0, SPI slave1, SPI master, FIFO-Asynchronous, FIFO- Synchronous, GPIO, debug interface and PWM. The I/O multiplexer allows the designer to select which peripherals are connected to the device I/O pins. ...
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... Figure 10-1. 4.2.11 Power Saving Modes and Standby mode. VNC2 can be set to operate in three frequencies allowing the user to select a slower speed to reduce power consumption. Three operating frequencies available are 12MHz, 24MHz and normal operation of 48MHz. These operating modes can be configured using the RTOS. Full details are available in the RTOS ...
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... UART, SPI slave0, SPI slave1, SPI master, FIFO, GPIO, and PWM peripherals. The available packages for VNC2 provide any of these interfaces to be active on the available pins through the use of an I/O Multiplexer. Table 8 lists the signals available for each peripheral. Table explain the use of the I/O multiplexer ...
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... Key: Group 0 allocated pin Group 1 allocated pin Group 2 allocated pin Group 3 allocated pin Figure 5-1 IOBUS to Group Relationship-64 Pin Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 Clearance No.: FTDI# IOBUS Pin IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 IOBUS5 IOBUS6 ...
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... Figure 5-2 IOBUS to UART, SPI slave0 and SPI master example Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 Clearance No.: FTDI# IOBUS Pin IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 IOBUS5 IOBUS6 IOBUS7 IOBUS8 ...
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... Figure 5-3 IOBUS to UART, SPI slave0 and SPI master second example Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 Clearance No.: FTDI# IOBUS Pin IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 IOBUS5 IOBUS6 IOBUS7 IOBUS8 ...
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... Figure 5-4 IOBUS to UART, SPI slave0 and SPI master third example Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 Clearance No.: FTDI# IOBUS Pin IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 IOBUS5 IOBUS6 IOBUS7 IOBUS8 ...
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... SPI clock input – master 1 1 Master out slave in - master 0 1 Master in slave out - master 1 0 Active low slave select 0 from master to slave Active low slave select 1 from master to slave Pulse width modulation Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 31 ...
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... Table 10 Group 1 Table 11 Group 2 Table 12 Group 3 Each VNC2 has a default state of IOBUS signals following a hard reset. The number of I/O pins available are determined by the package size: Package 32pin (LQFP & QFN)- Twelve I/O pins – IOBUS0 to IOBUS11 Package 48pin (LQFP & QFN)- Twenty eight I/O pins – IOBUS0 to IOBUS27 Package 64pin (LQFP & ...
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... Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 48 Pin Package 32 Pin Package Available Available pins pins 11, 15, 20, 31, 11, 23 35, 41 ...
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... Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 48 Pin 32 Pin Package Package Available Available pins pins 12,16, 12, 24, 21, 32, 30 36, 42 ...
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... Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 48 Pin 32 Pin Package Package Available Available pins pins 13, 18, 14, 25, 22, 33, 31 37, 43 ...
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... Available pins fifo_data[3] 14, 18, fifo_data[7] 23, 27, pwm[3] 32, 42, pwm[7] 46, 50, spi_m_ss_0# 56, 60, gpio[A3] 64 gpio[A7] gpio[B3] gpio[B7] gpio[C3] gpio[C7] gpio[D3] gpio[D7] gpio[E3] gpio[E7] Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 48 Pin 32 Pin Package Package Available Available pins pins 14, 19, 15, 26, 23, 34, 32 38, 44 ...
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... I/O Mux Interface Configuration Example This example shows how to set a UART interface on the VNC2 64 pin package. The UART is made up of two output signals (uart_txd and uart_rts#) and two input signals (uart_rxd and uart_cts#). For PCB design it is best to have the four pins of the UART interface adjacent to each other. This can be achieved easily since the four signals are members of each different groups ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 6 Peripheral Interfaces In addition to the two USB Host and Slave blocks, VNC2 contains the following peripheral interfaces: Universal Asynchronous Receiver Transmitter (UART) Two Serial Peripheral Interface (SPI) slaves SPI Master Debugger Interface Parallel FIFO Interface (245 mode and synchronous FIFO mode) ...
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... Input Receive asynchronous data input uart_rts# Output Request to send control output uart_cts# Input Clear to send control input Data acknowledge (data terminal uart_dtr# Output uart_dcd# Input Data carrier detect control input Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Description ready control) output 39 ...
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... UART signals. Further details on the configuration of input and output signals are available in Section 5 - I/O Multiplexer. Copyright © 2010 Future Technology Devices International Limited Name Type Ring indicator is used to wake VNC2 uart_ri# Input Enable transmit data for RS485 designs. This signal may be used to signal that a transmit operation is in progress ...
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... Master / Slave mode, with the Master initiating the data transfer. VNC2 has one master module and two slave modules. Each SPI slave module has four signals – clock, slave select, MOSI (master out – slave in) and MISO (master in – slave out). The SPI Master has the same four signals as the slave modules but with one additional signal because it requires a slave select for the second slave module ...
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... SCLK. Full Mode CPOL CPHA Duplex Table 16 - Clock Phase/Polarity Modes Figure 6-3 - SPI CPOL CPHA Function Copyright © 2010 Future Technology Devices International Limited Half Half Duplex Duplex Unmanged 4 pin 3 pin Document No.: FT_000138 Version - 143 Clearance No.: FTDI# VNC1L Legacy 1.2 42 ...
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... External - SPI Master Figure 6-4 SPI Slave block diagram VNC2 has two SPI Slave modules both of which use four wire interfaces: MOSI, MISO, CLK and SS#. Their main purpose is to send data from main memory to the attached SPI master, and / or receive data and send it to main memory ...
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... This continues until the Master indicates the end of the communications by raising SS#. Figure 6 example of this. Copyright © 2010 Future Technology Devices International Limited Name Type spi_s0_ss# spi_s1_ss# Input W0 W1 STATUS STATUS Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Description Slave chip select W2 STATUS 44 ...
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... Set to ‘1’ when a Slave has correctly decoded its address. Table 18 SPI Command and Status Fields Copyright © 2010 Future Technology Devices International Limited R0 STATUS Figure A0 R/ TXE RXF Description Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# R1 6-7 below with a description ACK Z 45 ...
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... Slave to the Master on the MOSI signal. Master to Slave SS# MOSI 8 bit CMD STATUS MISO Figure 6-9 Half Duplex Data Master Read Copyright © 2010 Future Technology Devices International Limited W0 W1 STATUS STATUS Slave to Master R0 R1 STATUS STATUS Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# W2 STATUS R2 STATUS 46 ...
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... Master to Slave SS# MOSI 8 bit CMD Figure 6-11 Half Duplex 3-pin Data Master Read Copyright © 2010 Future Technology Devices International Limited Slave to Master Master to Slave STATUS W0 Slave to Master STATUS R0 Document No.: FT_000138 Version - Clearance No.: FTDI# Slave to Master Master to Slave STATUS W1 STATUS R1 1.2 143 47 ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 6.3.5 Unmanaged Mode The VNC2 SPI Slave also supports an unmanaged SPI mode. This is a simple data exchange between Master and Slave. It operates in the standard 4 pin mode (SS#, CLK, MOSI and MISO) with all transfers controlled by the SPI Master. ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 6.3.6 VNC1L Legacy Interface VNC2 SPI is compatible with the SPI slave of VNC1L. This is a custom protocol using 4 wires and will be explained here. The Master asserts the slave select, but in this case active high signal. Following this bit command is sent on the MOSI pin (see Figure 6-15 for command structure) ...
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... When ‘0’ this means a read or write was successful. When ‘1’ it means a Status read contains old data write did not work and needs retried. Table 19 SPI Command and Status Fields Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 Clearance No.: FTDI# Description 1.2 Version - 143 50 ...
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... Table 20 SPI Setup Bit Encoding The VNC2 SPI interface uses 4 signal lines: SCLK, SS, MOSI and MISO. The signals MOSI, MISO and SS are always clocked on the rising edge of the SCLK signal. SS signal must be raised high for the duration of the entire transaction. For data transactions, the SS must be released for at least one clock cycle after a transaction has completed ...
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... The Start and Setup sequence is sent to VNC2 by the SPI master, see Figure 6-17. The VNC2 clocks out data from its Transmit Buffer on subsequent rising edge clock cycles provided by the SPI master. This is followed by a status bit generated by VNC2. The Data Read status bit is defined in Table 22. ...
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... VNC2, see Figure 6-18. This is followed by the SPI master transmitting each bit of the data to be written to VNC2. The VNC2 then responds with a status bit on MISO on the rising edge of the next clock cycle. The SPI master must read the status bit at the end of each write transaction to determine if the data was written successfully to VNC2 Receive Buffer ...
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... VNC2 and read the status byte. The Start and Setup sequence is sent to VNC2 by the SPI master, see Figure 6-19. The VNC2 clocks out its status byte on subsequent rising edge clock cycles from the SPI master. This is followed by a status bit generated by VNC2 (also on the MISO) which will always be zero (indicating new data) ...
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... An interface that‟s compatible with the VLSI VS1033 SCI mode used for VMUSIC capability The SPI Master only clocks in and out data that the VNC2 CPU sets up in its register space. The VNC2 CPU interprets the data words that are to be sent and received. ...
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... The main purpose of the SPI Master block is to transfer data between an external SPI interface and the VNC2. It does this under the control of the CPU and DMA engine via the on chip I/O bus. An SPI master interface transfer can only be initiated by the SPI Master and begins with the slave select signal being asserted ...
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... SCLK edge MISO hold time from sample t6 SCLK edge Table 26 SPI Master Timing Copyright © 2010 Future Technology Devices International Limited Minimum Typical Maximum 39.68 41.67 19.84 20.84 21.93 19.84 20.84 21.93 -1.5 3 6.5 0 Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Unit ...
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... Available pins pins pins 11, 15, 19, 24, 11, 15, 28, 39, 20, 31, 11, 23 43, 47, 35, 41, 29 51, 57 Table 27 Debugger Signal Name Copyright © 2010 Future Technology Devices International Limited Name Type Input/ debug_if Output Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Vinculum-II Description Debugger Interface 58 ...
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... Copyright © 2010 Future Technology Devices International Limited Name Type fifo_data[0] I/O fifo_data[1] I/O fifo_data[2] I/O fifo_data[3] I/O Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Description FIFO Data Bus Bit 0 FIFO Data Bus Bit 1 FIFO Data Bus Bit 2 FIFO Data Bus Bit 3 59 ...
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... Output When low, there is data available in the FIFO which can be read by strobing Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Description FIFO Data Bus Bit 4 FIFO Data Bus Bit 5 FIFO Data Bus Bit 6 FIFO Data Bus Bit 7 FIFO. fifo_rd# low, then high. ...
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... FIFO buffer when fifo_rd# goes from high Writes the data byte on the D0...D7 pins fifo_wr# Input into the transmit FIFO buffer when fifo_wr# goes from high to low. Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Description FIFO. to low 61 ...
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... It will only become low again when there is another byte to read. When FIFO_WR# goes low FIFO_TXE# flag will always go high. FIFO_TXE# goes low again only when there is still space for data to be written in to the module. Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 62 ...
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... DATA to TXE# active setup time DATA hold time after WR# t9 inactive t10 WR# active pulse width t11 WR# active after TXE# synchronous Table 29 A FIFO mode Read / Write Timing Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 Clearance No.: FTDI# Minimum Maximum Unit 100 ...
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... TXE# remains low when there is still space available for the data to be written. Copyright © 2010 Future Technology Devices International Limited Name Type fifo_oe# I/O FIFO Output enable fifo_clkout I/O Document No.: FT_000138 Version - Clearance No.: FTDI# Description FIFO Clock out 1.2 143 64 ...
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... OE# to read DATA valid t7 CLKOUT to OE# t8 RD# setup time t9 RD# hold time Copyright © 2010 Future Technology Devices International Limited Minimum Typical Maximum 20.83 9.38 10.42 9.38 10. Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Unit ns ns 11.46 11. 7.83 7. ...
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... WR# hold time ynchronous Table 31 S FIFO mode Read / Write Timing 6.8 General Purpose Timers In VNC2 there are 4 General Purpose Timers available. Three are available to the designer and one is reserved for the RTOS. The timers have the following features: 16 bit Count down ...
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... General Purpose Input Output VNC2 provides configurable Input/Output pins depending on the package. The Input/Output pins are connected to Ports A through E. These ports are controlled by the VNC2 CPU. All ports are configurable to be either inputs or outputs and allow level or edge driven interrupts to be generated. ...
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... USB 2.0 - 480Mb/s (High Speed) transactions shall not be supported as the power requirements are deemed excessive for VNC2 target applications. VNC2 configured to Full speed is supported. VNC2 has two main USB modes of operation: host mode or client (or Slave) mode client, VNC2 is able to connect and act like a USB device. At the same time as being a client the second USB interface is also able to act as a host and connect to a second USB device using two separate ports i.e. Port 0 – ...
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... RTOS The VNC2 RTOS (VOS pre-emptive priority-based multi-tasking operating system. VOS has been developed by FTDI and is available to customers for use in their own VNC2 based systems free of charge. VOS is supplied as linkable object files. A full explanation and how to use VOS is available in a separate application note which can be ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 8.3 Firmware – Software Development Tool Chain The VNC2 provides customers with the opportunity to customise the firmware and perform useful tasks without an external MCU. A Firmware application note is available to download from the FTDI website, this give further details and operating instructions. The VNC2 Software Development tool chain consists ...
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... VNC2 can be programmed with various pre-compiled firmware profiles to allow a designer to easily change the functionality of the chip. VNC2 is currently available with V2DAP firmware - V2DAP firmware: USB Host for single Flash Disk and general purpose USB peripherals. Selectable UART, FIFO or SPI interface command monitor. ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 9 Device Characteristics and Ratings 9.1 Absolute Maximum Ratings The absolute maximum ratings for VNC2 are shown in Table 32. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device. Parameter ...
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... TBD 8 128 Minimum Typical Maximum 2.4 0.4 1.5 Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Units Conditions Normal mA Operation mA Low Power Mode Lowest Power mA Mode µA USB Suspend Units Conditions V I source = 8mA V I sink = 8mA ...
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... Minimum Typical Maximum 1.62 1.8 1.98 1.62 1.8 1.98 -40 25 125 -10 ±1 10 -10 ±1 10 Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Units Conditions Ohms Units Conditions 1.8V power V supply 1.8V power V supply ° VCC18IO or in µA 0V µA 74 ...
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... Description Human Body Mode (HBM) Machine mode (MM) Charged Device Mode (CDM) Latch-up Table 37 ESD and Latch-up Specifications Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 Clearance No.: FTDI# Specification > ± 2kV > ± 200V > ± 500V > ± 200mA 1.2 Version - 143 ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 10 Application Examples 10.1 Example VNC2 Schematic (MCU – UART Interface) VNC2 can be configured to communicate with a microcontroller using a UART interface. An example of this is shown in Figure 10-1. Ferrite 3.3V LDO Bead Regulator 4.7uF 5V 100nF I G GND USB A ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 11 Package Parameters VNC2 is available in six RoHS Compliant packages, three QFN packages (64QFN, 48QFN & 32QFN) and three LQFP packages (64LQFP, 48LQFP & 32LQFP). All packages are lead (Pb) free and use a „green‟ compound. The packages are fully compliant with European Union directive 2002/95/EC. ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 11.2 VNC2, LQFP-32 Package Dimensions PIN #32 PIN #1 Figure 11-3 LQFP-32 Package Dimensions Copyright © 2010 Future Technology Devices International Limited FTDl XXXXXXXX VNC2-32L1A YYWW Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 78 ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 11.3 VNC2, QFN-32 Package Dimensions FTDl XXXXXXXX VNC2-32Q 1A YYWW 1 1 Figure 11-4 QFN-32 Package Dimensions Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 79 ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 11.4 VNC2, LQFP-48 Package Dimensions PIN# 48 Pin# 1 0.22+/- 0. Min 0. 15 Max Figure 11-5 LQFP-48 Package Dimensions Copyright © 2010 Future Technology Devices International Limited 9 7 FTDl XXXXXXXX VNC2-48L1A YYWW 0.5 1.0 o +/- Min 0. Min 0. 6 +/- 0.15 Document No ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 11.5 VNC2, QFN-48 Package Dimensions FTDl XXXXXXXXXX VNC2-48Q1A YYWW 1 1 Figure 11.2 QFN-48 Package Dimensions Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 81 ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 11.6 VNC2, LQFP-64 Package Dimensions Pin # 64 Pin # 0.05 0 0.15 x Figure 11-6 64 pin LQFP Package Details Copyright © 2010 Future Technology Devices International Limited 12 10 FTDl XXXXXXXX VNC2-64L1A YYWW 0 Document No.: FT_000138 1.2 Version - 143 Clearance No ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 11.7 VNC2, QFN-64 Package Dimensions FTDl XXXXXXXXXX VNC2-64Q1A YYWW Figure 11-7 64 pin QFN Package Details Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 83 ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet 11.8 Solder Reflow Profile Figure 11-8 All packages Reflow Solder Profile Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 84 ...
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... Max. p Volume mm3 < 350 235 +5/-0 deg C 220 +5/-0 deg C Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# SnPb Eutectic and Pb free (non green material) Solder Process 3°C / Second Max. 100°C 150° 120 seconds 183° 150 seconds see Table seconds 6° ...
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... Web Site URL http://www.ftdichip.com Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country. Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 1 ...
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... Table 32 Absolute Maximum Ratings ............................................................................................. 72 Table 33 Operating Voltage and Current ........................................................................................ 73 Table 34 I/O Pin Characteristics .................................................................................................... 73 Table 37 ESD and Latch-up Specifications ...................................................................................... 75 Table 38 Reflow Profile Parameter Values ...................................................................................... 85 Table 39 Package Reflow Peak Temperature ................................................................................... 85 Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# 87 ...
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... Figure 6-14 VNC1L Mode Data Read .............................................................................................. 49 Figure 6-15 VNC1L Compatible SPI Command and Status Structure .................................................. 49 Figure 6-16 SPI Slave Mode Timing ............................................................................................... 52 Figure 6-17 SPI Master Data Read (VNC2 Slave Mode) .................................................................... 53 Figure 6-18 SPI Slave Mode Data Write ......................................................................................... 54 Figure 6-19 SPI Slave Mode Status Read ....................................................................................... 54 Figure 6-20 SPI Master block diagram ...
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... VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet Figure 7-1 USB Modes ................................................................................................................. 68 Figure 10-1 VNC2 Schematic (MCU - UART Interface) ...................................................................... 76 Figure 11-1 Package Markings ...................................................................................................... 77 Figure 11-2 Markings – 32 QFN .................................................................................................... 77 Figure 11-3 LQFP-32 Package Dimensions ..................................................................................... 78 Figure 11-4 QFN-32 Package Dimensions ....................................................................................... 79 Figure 11-5 LQFP-48 Package Dimensions ..................................................................................... 80 Figure 11-6 64 pin LQFP Package Details ...
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... Revised Part Numbers section 1.2, note added to sections 3.12 and 5 – when I/O Mux is enabled the pins defaut to the values listed in table 6. Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000138 1.2 Version - 143 Clearance No.: FTDI# Feb 2010 th 26 Feb 2010 th 09 Sep 2010 ...