DSPIC30F3014-20I/PT Microchip Technology, DSPIC30F3014-20I/PT Datasheet - Page 30
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DSPIC30F3014-20I/PT
Manufacturer Part Number
DSPIC30F3014-20I/PT
Description
IC, DSC, 16BIT, 24KB 40MHZ, 5.5V, TQFP44
Manufacturer
Microchip Technology
Series
DsPIC30Fr
Datasheets
1.DSPIC30F3014-30IPT.pdf
(228 pages)
2.DSPIC30F3014-30IPT.pdf
(16 pages)
3.DSPIC30F3014-30IPT.pdf
(6 pages)
4.DSPIC30F3014-30IPT.pdf
(14 pages)
5.DSPIC30F3014-30IPT.pdf
(20 pages)
6.DSPIC30F3014-20IP.pdf
(226 pages)
Specifications of DSPIC30F3014-20I/PT
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
30
Interface Type
I2C/SPI/UART
On-chip Adc
13-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301420IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F3014-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F3014-20I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F3014/4013
3.2
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instructions),
or as one unified linear address range (for MCU instruc-
tions). The data spaces are accessed using two Address
Generation Units (AGUs) and separate data paths.
3.2.1
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent Linear
Addressing space, X and Y spaces have contiguous
addresses.
FIGURE 3-7:
DS70138F-page 28
Data Address Space
Optionally
Mapped
into Program
Memory
DATA SPACE MEMORY MAP
SRAM Space
2 Kbyte
SFR Space
2 Kbyte
dsPIC30F3014/dsPIC30F4013 DATA SPACE MEMORY MAP
Address
MSB
0x1FFF
0x0001
0x07FF
0x0801
0x0BFF
0x0C01
0x0FFF
0x1001
0x8001
0xFFFF
MSB
Unimplemented (X)
Y Data RAM (Y)
X Data RAM (X)
16 bits
SFR Space
X Data
When executing any instruction other than one of
the MAC class of instructions, the X block consists of the
64-Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions, the
X block consists of the 64-Kbyte data address space
excluding the Y address block (for data reads only). In
other words, all other instructions regard the entire data
memory as one composite address space. The MAC
class instructions extract the Y address space from data
space and address it using EAs sourced from W10 and
W11. The remaining X data space is addressed using W8
and W9. Both address spaces are concurrently accessed
only with the MAC class instructions.
The data space memory map is shown in Figure 3-7.
LSB
0x0000
0x07FE
0x0800
0x0BFE
0x0C00
0x0FFE
0x1000
0x1FFE
0x8000
0xFFFE
Address
LSB
© 2008 Microchip Technology Inc.
8 Kbyte
Near
Data
Space