DSPIC33FJ128MC804-E/ML Microchip Technology, DSPIC33FJ128MC804-E/ML Datasheet - Page 206

• Manufacturer Part Number: DSPIC33FJ128MC804-E/ML
• Description: IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN44
• Manufacturer: Microchip Technology
• Series: DsPIC33Fr

Specifications of DSPIC33FJ128MC804-E/ML

• Core Frequency: 40MHz
• Core Supply Voltage: 3.6V
• No. Of I/o's: 35
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +125°C
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

15.1
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 15-1 lists the different bit settings for the Output
Compare modes. Figure 15-2 illustrates the output
compare operation for various modes. The user
application must disable the associated timer when
writing to the output compare control registers to avoid
malfunctions.
TABLE 15-1:
FIGURE 15-2:
DS70291D-page 206
OCM<2:0>
Continuous Pulse Mode
000
001
010
011
100
101
110
111
Active High One-Shot
Active Low One-Shot
(OCM = 110 or 111)
Delayed One-Shot
Output Compare Modes
(OCM = 011)
(OCM = 100)
Toggle Mode
(OCM = 101)
(OCM = 001)
(OCM = 010)
PWM Mode
Module Disabled
Active-Low One-Shot
Active-High One-Shot
Toggle Mode
Delayed One-Shot
Continuous Pulse mode
PWM mode without fault
protection
PWM mode with fault protection 0, if OCxR is zero
OUTPUT COMPARE MODES
TMRy
OUTPUT COMPARE OPERATION
OCxRS
OCxR
Mode
Output Compare
Mode enabled
Current output is maintained
0, if OCxR is zero
1, if OCxR is non-zero
1, if OCxR is non-zero
Controlled by GPIO register
Preliminary
OCx Pin Initial State
Timer is reset on
period match
0
1
0
0
Note 1: Only OC1 and OC2 can trigger a DMA
2: See Section 13. “Output Compare” in
data transfer.
the “dsPIC33F/PIC24H Family Reference
Manual” (DS70209) for OCxR and
OCxRS register restrictions.
OCx Rising edge
OCx Falling edge
OCx Rising and Falling edge
OCx Falling edge
OCx Falling edge
No interrupt
OCFA Falling edge for OC1 to OC4
OCx Interrupt Generation
© 2009 Microchip Technology Inc.
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