DSPIC30F2012-30I/ML Microchip Technology, DSPIC30F2012-30I/ML Datasheet - Page 93
![IC, DSC, 16BIT, 12KB, 40MHZ, 5.5V, QFN28](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F2012-30I/ML
Manufacturer Part Number
DSPIC30F2012-30I/ML
Description
IC, DSC, 16BIT, 12KB, 40MHZ, 5.5V, QFN28
Manufacturer
Microchip Technology
Series
DsPIC30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F2012-30I/ML
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Package
28QFN EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
12
Interface Type
I2C/SPI/UART
On-chip Adc
10-chx12-bit
Number Of Timers
3
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F201230IML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2012-30I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
13.0
The Serial Peripheral Interface (SPI™) module is a
synchronous
communicating with other peripheral devices, such as
EEPROMs, shift registers, display drivers and A/D
converters, or other microcontrollers. It is compatible
with Motorola's SPI and SIOP interfaces. The
dsPIC30F2011/2012/3012/3013 devices feature one
SPI module, SPI1.
13.1
Figure 13-1
module, which consists of a 16-bit shift register,
SPI1SR, used for shifting data in and out, and a buffer
register, SPI1BUF. Control register SPI1CON (not
shown) configures the module. Additionally, status
register SPI1STAT (not shown) indicates various status
conditions.
Four I/O pins comprise the serial interface:
• SDI1 (serial data input)
• SDO1 (serial data output)
• SCK1 (shift clock input or output)
• SS1 (active-low slave select).
© 2010 Microchip Technology Inc.
Note:
Note:
SPI™ MODULE
Operating Function Description
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
See
Manual”
information on the control and status
registers.
is a simplified block diagram of the SPI
serial
“dsPIC30F
interface.
(DS70046)
Family
It
for
dsPIC30F2011/2012/3012/3013
is
Reference
useful
detailed
for
In Master mode operation, SCK1 is a clock output. In
Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shift
out bits from the SPI1SR to SDO1 pin and
simultaneously shift in data from SDI1 pin. An interrupt
is generated when the transfer is complete and the
interrupt flag bit (SPI1IF) is set. This interrupt can be
disabled through the interrupt enable bit, SPI1IE.
The receive operation is double-buffered. When a
complete byte is received, it is transferred from SPI1SR
to SPI1BUF.
If the receive buffer is full when new data is being
transferred from SPI1SR to SPI1BUF, the module will
set the SPIROV bit indicating an overflow condition.
The transfer of the data from SPI1SR to SPI1BUF is not
completed and the new data is lost. The module will not
respond to SCL transitions while SPIROV is ‘1’, effec-
tively disabling the module until SPI1BUF is read by
user software.
Transmit writes are also double-buffered. The user
writes to SPI1BUF. When the master or slave transfer
is completed, the contents of the shift register
(SPI1SR) are moved to the receive buffer. If any
transmit data has been written to the buffer register, the
contents of the transmit buffer are moved to SPI1SR.
The received data is thus placed in SPI1BUF and the
transmit data in SPI1SR is ready for the next transfer.
Note:
Both the transmit buffer (SPI1TXB) and
the receive buffer (SPI1RXB) are mapped
to the same register address, SPI1BUF.
DS70139G-page 93