DSPIC30F2012-30I/ML Microchip Technology, DSPIC30F2012-30I/ML Datasheet - Page 95
![IC, DSC, 16BIT, 12KB, 40MHZ, 5.5V, QFN28](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F2012-30I/ML
Manufacturer Part Number
DSPIC30F2012-30I/ML
Description
IC, DSC, 16BIT, 12KB, 40MHZ, 5.5V, QFN28
Manufacturer
Microchip Technology
Series
DsPIC30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F2012-30I/ML
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Package
28QFN EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
12
Interface Type
I2C/SPI/UART
On-chip Adc
10-chx12-bit
Number Of Timers
3
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F201230IML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2012-30I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
FIGURE 13-2:
13.3
The SS1 pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SS1
pin control enabled (SSEN = 1). When the SS1 pin is
low, transmission and reception are enabled and the
SDOx pin is driven. When SS1 pin goes high, the
SDOx pin is no longer driven. Also, the SPI module is
resynchronized, and all counters/control circuitry are
reset. Therefore, when the SS1 pin is asserted low
again, transmission/reception will begin at the MSb
even if SS1 had been de-asserted in the middle of a
transmit/receive.
13.4
During Sleep mode, the SPI module is shut down. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.
© 2010 Microchip Technology Inc.
Slave Select Synchronization
SPI Operation During CPU Sleep
Mode
MSb
PROCESSOR 1
Serial Input Buffer
SPI MASTER/SLAVE CONNECTION
SPI Master
Shift Register
(SPI1BUF)
(SPI1SR)
LSb
dsPIC30F2011/2012/3012/3013
SDO1
SCK1
SDI1
Serial Clock
13.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPI1STAT<13>)
selects if the SPI module will stop or continue on idle. If
SPISIDL = 0, the module will continue to operate when
the CPU enters Idle mode. If SPISIDL = 1, the module
will stop when the CPU enters Idle mode.
SDO1
SCK1
SDI1
SPI Operation During CPU Idle
Mode
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SPI1BUF)
(SPI1SR)
SPI Slave
LSb
DS70139G-page 95