ADSP-21161NKCA-100 Analog Devices Inc, ADSP-21161NKCA-100 Datasheet - Page 14

• Manufacturer Part Number: ADSP-21161NKCA-100
• Description: IC, FLOAT-PT DSP, 32BIT, 100MHZ, MBGA225
• Manufacturer: Analog Devices Inc
• Series: SHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCA-100

• No. Of Bits: 32 Bit
• Frequency: 100MHz
• Supply Voltage: 1.8V
• Embedded Interface Type: HPI, SPI
• No. Of I/o's: 12
• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADSP-21161NKCA100

ADSP-21161N
Table 2. Pin Function Descriptions (Continued)
Pin
DMAR1
DMAR2
DMAG1
DMAG2
BR6–1
BMSTR
ID2–0
RPBA
PA
DxA
DxB
SCLKx
FSx
SPICLK
Type
I/A
I/A
O/T
O/T
I/O/S
O
I
I/S
I/O/T
I/O
I/O
I/O
I/O
I/O
Function
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services. DMAR1 has
a 20 k internal pull-up resistor that is enabled for DSPs with ID2–0=00x.
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has
a 20 k internal pull-up resistor that is enabled for DSPs with ID2–0=00x.
DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21161N to indicate that the requested DMA starts on the
next cycle. Driven by bus master only. DMAG1 has a 20 k internal pull-up resistor that is enabled for DSPs
with ID2–0=00x.
DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21161N to indicate that the requested DMA starts on the
next cycle. Driven by bus master only. DMAG2 has a 20 k internal pull-up resistor that is enabled for DSPs
with ID2–0=00x.
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21161Ns to arbitrate for bus mastership. An
ADSP-21161N only drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all
others. In a multiprocessor system with less than six ADSP-21161Ns, the unused BRx pins should be pulled
high; the processor's own BRx line must not be pulled high or low because it is an output.
Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21161N is current bus master
of the shared external bus. The ADSP-21161N drives BMSTR high only while it is the bus master. In a single-
processor system (ID=000), the processor drives this pin high. This pin is used for debugging purposes.
Multiprocessing ID. Determines which multiprocessing bus request (BR6–BR1) is used by ADSP-21161N.
ID=001 corresponds to BR1, ID=010 corresponds to BR2, and so on. Use ID=000 or ID=001 in single-
processor systems. These lines are a system configuration selection that should be hardwired or only changed
at reset.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration
selection that must be set to the same value on every ADSP-21161N. If the value of RPBA is changed during
system operation, it must be changed in the same CLKIN cycle on every ADSP-21161N.
Priority Access. Asserting its PA pin enables an ADSP-21161N bus slave to interrupt background DMA
transfers and gain access to the external bus. PA is connected to all ADSP-21161Ns in the system. If access
priority is not required in a system, the PA pin should be left unconnected. PA has a 20 k internal pull-up
resistor that is enabled for DSPs with ID2–0=00x.
Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has an internal pull-up resistor.
Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to
receive serial data.
Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has an internal pull-up resistor.
Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to
receive serial data.
Transmit/Receive Serial Clock (Serial Ports 0, 1, 2, 3). Each SCLK pin has an internal pull-up resistor. This
signal can be either internally or externally generated.
Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates shifting of serial data.
This signal is either generated internally or externally. It can be active high or low or an early or a late frame
sync, in reference to the shifting of serial data.
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is
transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit trans-
mitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word.
Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge
of the clock and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data
are programmable into the SPICTL control register and define the transfer format. SPICLK has a 50 k internal
pull-up resistor.
Rev. B | Page 14 of 60 | November 2009