ADSP-21161NKCA-100 Analog Devices Inc, ADSP-21161NKCA-100 Datasheet - Page 47

• Manufacturer Part Number: ADSP-21161NKCA-100
• Description: IC, FLOAT-PT DSP, 32BIT, 100MHZ, MBGA225
• Manufacturer: Analog Devices Inc
• Series: SHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-21161NKCA-100

• No. Of Bits: 32 Bit
• Frequency: 100MHz
• Supply Voltage: 1.8V
• Embedded Interface Type: HPI, SPI
• No. Of I/o's: 12
• Supply Voltage Range: 1.71V To 1.89V, 3.13V To 3.47V
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-MBGA, 225-Mini-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADSP-21161NKCA100

Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 30. Serial Ports — External Clock
1
Table 31. Serial Ports — Internal Clock
1
Table 32. Serial Ports — External Clock
1
2
3
Table 33. Serial Ports — Internal Clock
1
2
3
Parameter
Timing Requirements
t
t
t
t
t
t
Referenced to sample edge.
Parameter
Timing Requirements
t
t
t
t
Referenced to sample edge.
Parameter
Switching Characteristics
t
t
t
t
Referenced to drive edge.
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.
Parameter
Switching Characteristics
t
t
t
t
t
Referenced to drive edge.
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
SFSI
HFSI
SDRI
HDRI
DFSE
HOFSE
DDTE
HDTE
DFSI
HOFSI
DDTI
HDTI
SCLKIW
FS Delay After SCLK (Internally Generated FS)
FS Hold After SCLK (Internally Generated FS)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
SCLK Width
Transmit/Receive FS Setup Before Transmit/Receive SCLK
Transmit/Receive FS Hold After Transmit/Receive SCLK
Receive Data Setup Before Receive SCLK
Receive Data Hold After Receive SCLK
SCLKx Width
SCLKx Period
FS Setup Time Before SCLK (Transmit/Receive Mode)
FS Hold After SCLK (Transmit/Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
FS Delay After SCLK (Internally Generated FS)
FS Hold After SCLK (Internally Generated FS)
2
1
1, 2
1, 2
1, 2
1, 2
Rev. B | Page 47 of 60 | November 2009
1
1
1
1, 2 , 3
1, 2, 3
1
1, 2, 3
1, 2, 3
1
1
1
Min
3
0
100 MHz
Min
8
0.5t
4
3
Min
3.5
2
1.5
4
7
2t
Min
–1.5
0
0.5t
CCLK
CCLK
SCLK
Max
13
16
+1
–2.5
Min
2.75
0
Max
Max
Max
4.5
7.5
0.5t
110 MHz
SCLK
ADSP-21161N
+2
Max
13
16
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns