ISPLSI1032E-70LJN LATTICE SEMICONDUCTOR, ISPLSI1032E-70LJN Datasheet - Page 13

• Manufacturer Part Number: ISPLSI1032E-70LJN
• Description: CMOS ISP EEPLD, SMD, 1032, PLCC84
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI1032E-70LJN

• No. Of Macrocells: 128
• No. Of I/o's: 64
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 11ns
• Frequency: 70MHz
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Logic: RoHS Compliant

Pin Description
1. NC pins are not to be connected to any active signals, Vcc or GND.
2. Pins have dual function capability.
3. Pins have dual function capability which is software selectable.
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
GOE 0/IN 4
GOE 1/IN 5
IN 6, IN 7
ispEN
SDI/IN 0
MODE/IN 1
SDO/IN 2
SCLK/IN 3
RESET
Y0
Y1
Y2
Y3
GND
VCC
NC
NAME
1
2
2
2
3
3
2
26,
30,
34,
38,
45,
49,
53,
57,
68,
72,
76,
80,
3,
7,
11,
15,
67
84
2,
23
25
42
44
61
24
20
66
63
62
1,
21, 65
NUMBERS
PLCC PIN
22, 43, 64
27,
31,
35,
39,
46,
50,
54,
58,
69,
73,
77,
81,
4,
8,
12,
16,
19
28,
32,
36,
40,
47,
51,
55,
59,
70,
74,
78,
82,
5,
9,
13,
17,
29,
33,
37,
41,
48,
52,
56,
60,
71,
75,
79,
83,
6,
10,
14,
18
17,
21,
29,
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
66
87
89,
14
16
37
12,
1,
26,
51,
76,
39
60
15
11
65
62
61
13, 38, 63, 88
6,
NUMBERS
TQFP PIN
64
2,
27,
52,
77,
18,
22,
30,
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
10
3,
7,
24, 25,
49, 50,
74, 75,
99, 100
19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
8,
20,
28,
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
9
Input/Output Pins - These are the general purpose I/O pins used by the logic
array.
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
Dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK options become active.
Input - This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. SDI/IN 0 is also
used as one of the two control pins for the isp state machine. It is a
dedicated input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it functions
as pin to control the operation of the isp state machine. It is a dedicated
input pin when ispEN is logic high.
Output/Input - This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it functions
as a clock pin for the Serial Shift Register. It is a dedicated input pin when
ispEN is logic high.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the
device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB on the device.
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB and/or any I/O cell on the
device.
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any I/O cell on the device.
Ground (GND)
Vcc
No connect.
13
Specifications ispLSI 1032E
DESCRIPTION
Table 2-0002A/1032E