CAT24C05WI-GT3 CATALYST SEMICONDUCTOR, CAT24C05WI-GT3 Datasheet - Page 8

• Manufacturer Part Number: CAT24C05WI-GT3
• Description: IC, EEPROM, 4KBIT, SERIAL, 400KHZ SOIC-8
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT24C05WI-GT3

• Memory Size: 4Kbit
• Memory Configuration: 512 X 8 / 256 X 16
• Ic Interface Type: I2C
• Clock Frequency: 400kHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Immediate Read
the CAT24C03/05 will interpret this as a request for data
residing at the current byte address in memory. The
CAT24C03/05 will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24C03/05
returns to Standby mode.
Selective Read
select at random any memory location for a read operation.
The Master device first performs a ‘dummy’ write operation
by sending the START condition, slave address and byte
Upon receiving a Slave address with the R/W bit set to ‘1’,
Selective Read operations allow the Master device to
BUS ACTIVITY:
MASTER
SCL
SDA
BUS ACTIVITY:
SLAVE
MASTER
SLAVE
ADDRESS
SLAVE
S
S
A
R
T
T
BUS ACTIVITY:
C
A
K
Figure 10. Immediate Read Sequence and Timing
ADDRESS
SLAVE
MASTER
SLAVE
BYTE
D ATA
Figure 12. Sequential
Figure 11.
DATA OUT
n
8
8
th
Bit
S
A
C
K
R
S
T
A
T
READ OPERATIONS
http://onsemi.com
A
C
K
ADDRESS
Selective
ADDRESS
BYTE
SLAVE
BYTE
D ATA
n+1
8
Read Sequence
address of the location it wishes to read. After the
CAT24C03/05 acknowledges the byte address, the Master
device resends the START condition and the slave address,
this time with the R/W bit set to one. The CAT24C03/05 then
responds with its acknowledge and sends the requested data
byte. The Master device does not acknowledge the data
(NoACK) but will generate a STOP condition (Figure 11).
Sequential Read
data byte, then the CAT24C03/05 will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wrap−around at end of memory (rather than end of page).
Read
If during a Read session, the Master acknowledges the 1
A
C
K
A
C
K
NO ACK
S
A
R
S
T
T
C
A
K
9
Sequence
ADDRESS
BYTE
D ATA
SLAVE
BYTE
D ATA
n+2
N
O
A
C
K
A
C
K
P
S
O
P
T
C
A
K
BYTE
D ATA
STOP
BYTE
D ATA
n+x
O
N
A
C
K
P
O
S
T
P
O
N
A
C
K
O
S
T
P
P
st