25AA1024-I/SN Microchip Technology, 25AA1024-I/SN Datasheet - Page 15

• Manufacturer Part Number: 25AA1024-I/SN
• Description: IC, EEPROM, 1MBIT, SERIAL, 20MHZ, SOIC-8
• Manufacturer: Microchip Technology

Specifications of 25AA1024-I/SN

• Memory Size: 1Mbit
• Ic Interface Type: SPI
• Clock Frequency: 20MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Memory Configuration: 128K X 8

2.8
The Page Erase function will erase all bits (FFh) inside
the given page. A Write Enable (WREN) instruction
must be given prior to attempting a Page Erase. This
is done by setting CS low and then clocking out the
proper instruction into the 25AA1024. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
The Page Erase function is entered by driving CS low,
followed by the instruction code (Figure 2-8), and
three address bytes. Any address inside the page to
be erased is a valid address.
FIGURE 2-8:
 2010 Microchip Technology Inc.
PAGE ERASE
SCK
SO
CS
SI
PAGE ERASE SEQUENCE
0
0
1
1
0
Instruction
2
0
3
0
4
0
5
High-Impedance
1
6
0
7
23 22 21 20
8
CS must then be driven high after the last bit if the
address or the Page Erase will not execute. Once the
CS is driven high, the self-timed Page Erase cycle is
started. The WIP bit in the STATUS register can be
read to determine when the Page Erase cycle is
complete.
If a Page Erase function is given to an address that
has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
9 10 11
24-bit Address
29 30 31
2
1
0
25AA1024
DS21836G-page 15