NTE2732A NTE ELECTRONICS, NTE2732A Datasheet - Page 3

• Manufacturer Part Number: NTE2732A
• Description: IC, EPROM, 32KBIT, 200NS, DIP-24
• Manufacturer: NTE ELECTRONICS

Specifications of NTE2732A

• Memory Size: 32Kbit
• Memory Configuration: 4K X 8
• Access Time: 200ns
• Supply Voltage Range: 4.75V To 5.25V
• Memory Case Style: DIP
• No. Of Pins: 24
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AC Waveforms:
Note 6. OE may be delayed up to t
Note 7. t
Read Mode:
The NTE2732A has two control functions, both of which must be logically satisfied in order to obtain
data at the outputs. Chip Enable (CE) is the power control and should be used for device selection.
Output Enable (OE) is the output control and should be used to gate data to the output pins, indepen-
dent of device selection.
Assuming that addresses are stable, address access time (t
(t
and addresses have been stable for at least t
Standby Mode:
The NTE2732A has a standby mode which reduces the active power current by 70%, from 125mA
to 35mA. The NTE2732A is placed in the standby mode by applying a TTL high signal to CE input.
When in standby mode, the outputs are in a high impedance state, independent of the OE input.
Output OR–Tieing:
Because NTE2732A’s are usually used in larger memory arrays, the product features a 2 line control
function which accommodates the use of multiple memory connection. The two line control function
allows:
To most efficiently use these two control lines, it is recommended that CE be decoded and used as
the primary device selecting function, while OE should be made a common connection to all devices
in the array and connected to the READ line from the system control bus.
This assures that all deselected memory devices are in their low power standby mode and that the
output pins are only active when data is desired from a particular memory device.
CE
). Data is available at the outputs after the falling edge of OE, assuming that CE has been low
a) the lowest possible memory power dissipation
b) complete assurance that output bus contention will not occur
ADDRESSES
DF
OUTPUT
is specified from OE or CE whichever occurs first.
OE
CE
HIGH Z
ADDRESSES VALID
t
ACC
ACC
t
CE
– t
t
DE
OE
(Note 6)
ACC
after the falling edge CE without impact on t
–t
OE
.
ACC
VALID OUTPUT
) is equal to delay from CE to output
t
DE
t
OH
(Note 7)
HIGH Z
ACC
.