SST25VF080B-50-4I-S2AF SILICON STORAGE TECHNOLOGY, SST25VF080B-50-4I-S2AF Datasheet - Page 5

• Manufacturer Part Number: SST25VF080B-50-4I-S2AF
• Description: IC, FLASH, 8MBIT, 50MHZ, SOIC-8
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25VF080B-50-4I-S2AF

• Memory Type: Flash
• Memory Size: 8Mbit
• Memory Configuration: 1M X 8
• Ic Interface Type: SPI
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8 Mbit SPI Serial Flash
SST25VF080B
Hold Operation
The HOLD# pin is used to pause a serial sequence under-
way with the SPI flash memory without resetting the clock-
ing sequence. To activate the HOLD# mode, CE# must be
in active low state. The HOLD# mode begins when the
SCK active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
Write Protection
SST25VF080B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP3, BP2, BP1, BP0, and BPL) in the status register pro-
vide Write protection to the memory array and the status
register. See Table 4 for the Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 2). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
©2006 Silicon Storage Technology, Inc.
HOLD#
FIGURE 3: H
SCK
OLD
Active
C
ONDITION
W
AVEFORM
Hold
5
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
23 for Hold timing.
TABLE 2: C
WP#
H
L
L
Active
R
ONDITIONS TO EXECUTE
EGISTER
BPL
X
1
0
Hold
(WRSR) I
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
NSTRUCTION
S71296-01-000
Active
W
RITE
1296 HoldCond.0
IL
Data Sheet
or V
-S
TATUS
IH.
T2.0 1296
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