SST25VF080B-50-4C-PAE SST [Silicon Storage Technology, Inc], SST25VF080B-50-4C-PAE Datasheet
SST25VF080B-50-4C-PAE
Related parts for SST25VF080B-50-4C-PAE
SST25VF080B-50-4C-PAE Summary of contents
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... Erase or Program operation is less than alternative flash memory technologies. The SST25VF080B device is offered in 8-lead SOIC (200 mils), 8-contact WSON (6mm x 5mm), and 8-lead PDIP (300 mils) packages. See Figure 2 for pin assignments. ...
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... Data Sheet Address Buffers and Latches CE# FIGURE 1: Functional Block Diagram ©2010 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD Mbit SPI Serial Flash SST25VF080B SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1296 B1.0 S71296-04-000 01/10 ...
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... The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. V Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF080B DD V Ground SS ©2010 Silicon Storage Technology, Inc ...
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... Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF080B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... HOLD# Active FIGURE 4: Hold Condition Waveform Write Protection SST25VF080B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register pro- vide Write protection to the memory array and the status register ...
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... Default at Power- Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit pro- vides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. 6 SST25VF080B Read/Write R R R/W R/W R/W R/W R R/W T3.0 1296 S71296-04-000 01/10 ...
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... WP# is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block- Protection bits are all 0. After power-up, BP3, BP2, BP1 and BP0 are set to 1. TABLE 4: Software Status Register Block Protection for SST25VF080B Protection Level None Upper 1/16 Upper 1/8 ...
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... Data Sheet Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF080B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instruc- tions, the Write-Enable (WREN) instruction must be exe- cuted first ...
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... The Read instruction, 03H, supports MHz (for SST25VF080B-50-xx-xxxx) or SST25VF080B-80-xx-xxxx) Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until ter- minated by a low to high transition on CE#. The internal address pointer will automatically increment until the high- est memory address is reached ...
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... FFFFFH has been read, the next output will be from address location 00000H ADD. ADD. ADD. X MSB MSB Mbit SPI Serial Flash SST25VF080B N+1 N+2 N+3 N OUT OUT OUT OUT OUT 1296 HSRdSeq ...
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... Mbit SPI Serial Flash SST25VF080B Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a pro- tected memory area will be ignored. ...
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... SCK =1. CE# must be 0 FIGURE 8: Enable SO as Hardware RY/BY# CE# SCK FIGURE 9: Disable SO as Hardware RY/BY Mbit SPI Serial Flash SST25VF080B MODE MODE MSB SO HIGH IMPEDANCE 1296 EnableSO.0 during AAI Programming MODE ...
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... Mbit SPI Serial Flash SST25VF080B CE MODE 3 SCK MODE Load AAI command, Address, 2 bytes data SO Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming ...
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... Most ADD. ADD. MSB MSB HIGH IMPEDANCE 14 8 Mbit SPI Serial Flash SST25VF080B ), remaining address bits can for the completion of the internal self-timed ADD. 1296 SecErase.0 S71296-04-000 IH. 01/10 ...
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... Mbit SPI Serial Flash SST25VF080B 32-KByte and 64-KByte Block-Erase The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored ...
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... CE#. See Figure 16 for the RDSR instruction sequence Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB 16 8 Mbit SPI Serial Flash SST25VF080B Status Register Out 1296 RDSRseq.0 S71296-04-000 CE 01/10 ...
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... Mbit SPI Serial Flash SST25VF080B Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- Enable-Latch bit in the Status Register to 1 allowing Write operations to occur. The WREN instruction must be exe- cuted prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow execution of ...
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... BP2 bits at the same time. See Table 2 for a summary description of WP# and BPL functions MODE 3 MODE 0 STATUS REGISTER MSB MSB HIGH IMPEDANCE 18 SST25VF080B ) prior to the IH 1296 EWSR.0 S71296-04-000 01/10 ...
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... SST25VF080B JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as SST25VF080B and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin ...
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... Data Sheet Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as SST25VF080B and manufacturer as SST. This command is backward compatible and should be used as default device identification when multiple versions of SPI Serial Flash devices are used in a design. The device information can be read from executing an 8-bit command, 90H or ...
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... Output shorted for no more than one second. No more than one output shorted at a time. Operating Range Range Ambient Temp Commercial 0°C to +70°C Industrial -40°C to +85°C TABLE 8: DC Operating Characteristics (SST25VF080B-50-xx-xxxx) Symbol Parameter I Read Current DDR I Read Current DDR2 ...
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... Data Sheet TABLE 9: DC Operating Characteristics (SST25VF080B-80-xx-xxxx) Symbol Parameter I Read Current DDR I Read Current DDR3 I Program and Erase Current DDW I Standby Current SB I Input Leakage Current LI I Output Leakage Current LO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage ...
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... Mbit SPI Serial Flash SST25VF080B TABLE 13: AC Operating Characteristics (SST25VF080B-50-xx-xxxx) Symbol Parameter 3 F Serial Clock Frequency CLK T Serial Clock High Time SCKH T Serial Clock Low Time SCKL 4 T Serial Clock Rise Time (Slew Rate) SCKR T Serial Clock Fall Time (Slew Rate) ...
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... Data Sheet TABLE 14: AC Operating Characteristics (SST25VF080B-80-xx-xxxx) Symbol Parameter 1 F Serial Clock Frequency CLK T Serial Clock High Time SCKH T Serial Clock Low Time SCKL 2 T Serial Clock Rise Time (Slew Rate) SCKR T Serial Clock Fall Time (Slew Rate) SCKF 3 T CE# Active Setup Time ...
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... Mbit SPI Serial Flash SST25VF080B CE CHH CES SCK MSB SI SO HIGH-Z FIGURE 22: Serial Input Timing Diagram CE# T SCKH SCK T CLZ SO SI FIGURE 23: Serial Output Timing Diagram ©2010 Silicon Storage Technology, Inc. T SCKF T SCKR T SCKL T OH MSB Data Sheet ...
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... Commands may not be accepted or properly interpreted by the device. V Min DD FIGURE 25: Power-up Timing Diagram ©2010 Silicon Storage Technology, Inc HHS HHH HLS T HLH PU-READ Device fully accessible T PU-WRITE 26 8 Mbit SPI Serial Flash SST25VF080B T LZ 1296 Hold.0 Time 1296 PwrUp.0 S71296-04-000 01/10 ...
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... Mbit SPI Serial Flash SST25VF080B V IHT INPUT V ILT AC test inputs are driven at V (0.9V IHT for inputs and outputs are V (0.6V HT FIGURE 26: AC Input/Output Reference Waveforms FIGURE 27: A Test Load Example ©2010 Silicon Storage Technology, Inc REFERENCE POINTS for a logic “1” and V (0 ...
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... Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”. 2. Environmental suffix “F” denotes non-Pb/non-SN solder. SST non-Pb/non-Sn solder devices are “RoHS Compliant”. SST25VF080B-50-4C-PAE 28 8 Mbit SPI Serial Flash SST25VF080B S71296-04-000 ...
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... Mbit SPI Serial Flash SST25VF080B PACKAGING DIAGRAMS Pin #1 TOP VIEW Identifier 5.40 5.15 5.40 5.15 8.10 7.70 Note: 1. All linear dimensions are in millimeters (max/min). 2. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads. FIGURE 28: 8-lead Small Outline Integrated Circuit (SOIC) 200 mil body width (5.2mm x 8mm) SST Package Code: S2A © ...
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... FIGURE 29: 8-contact Very-very-thin Small Outline No-lead (WSON) SST Package Code: QA ©2010 Silicon Storage Technology, Inc. SIDE VIEW 0.2 5.00 ± 0.10 0.076 0.05 Max 0.80 0.70 leads. 1mm SS of the unit Mbit SPI Serial Flash SST25VF080B BOTTOM VIEW Pin #1 1.27 BSC 4.0 0.48 0.35 3.4 0.70 0.50 CROSS SECTION 0.80 0.70 8-wson-5x6-QA-9.0 S71296-04-000 01/10 ...
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... Mbit SPI Serial Flash SST25VF080B TOP VIEW 0.355 0.400 Pin 1 SIDE VIEW 0.056 0.064 0.115 0.150 0.014 0.022 0.100 BSC Note: 1. Complies with JEDEC publication 95 MS-001 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. ...
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... Added Table 9 on page 22 and Table 14 on page 24 • Edited Product Ordering Information • Added Valid Combinations SST25VF080B-80-4C-S2AE, SST25VF080B-80-4I- S2AE, SST25VF080B-80-4C-QAE, and SST25VF080B-80-4I-QAE Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2010 Silicon Storage Technology, Inc. ...