A29040BL-70F AMIC, A29040BL-70F Datasheet - Page 12

• Manufacturer Part Number: A29040BL-70F
• Description: IC, SM, FLASH, 4MB, 5V
• Manufacturer: AMIC

Specifications of A29040BL-70F

• Memory Size: 4Mbit
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: PLCC
• No. Of Pins: 32
• Access Time: 70ns
• Interface: Parallel
• Logic Function Number: 29040
• Memory Configuration: 512K X
• Package / Case: PLCC
• Memory Type: Uniform Sector Flash
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write Operation Status
Several bits, I/O
the A29040B to determine the status of a write operation.
Table 5 and the following subsections describe the functions
of these status bits. I/O
for determining whether a program or erase operation is
complete or in progress. These three bits are discussed first.
I/O
The
whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Polling is valid after the rising edge of the final
the program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O
This I/O
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O
The system must provide the program address to read valid
status information on I/O
protected sector,
approximately 2µs, then the device returns to reading array
data.
During the Embedded Erase algorithm,
produces a "0" on I/O
is complete, or if the device enters the Erase Suspend mode,
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected,
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O
complement to true data, it can read valid data at I/O
on the following read cycles. This is because I/O
change asynchronously with I/O
(
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 5 shows the outputs for
Polling on I/O
(January, 2007, Version 1.0)
Data
OE
7
: Data Polling
Data
) is asserted low. The
Polling produces a "1" on I/O
7
the complement of the datum programmed to I/O
7
status also applies to programming during Erase
Polling bit, I/O
7
. Figure 3 shows the
2
, I/O
Data
7
3
. When the Embedded Erase algorithm
, I/O
7
7
7
, I/O
.
. If a program address falls within a
7
Polling on I/O
5
, indicates to the host system
, I/O
6
Data
and I/O
0
6
7
, and I/O
- I/O
7
Data
has changed from the
.This is analogous to the
Polling Timings (During
Data
2
6
each offer a method
while Output Enable
Polling algorithm.
Polling on I/O
7,
7
are provided in
is active for
Data
WE
pulse in
Polling
7
7
Data
Data
- I/O
may
7
is
7
7
0
.
.
11
Note :
1. VA = Valid address for programming. During a sector
2. I/O
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
I/O
No
7
7
should be rechecked even if I/O
may change simultaneously with I/O
Figure 3. Data Polling Algorithm
Read I/O
Read I/O
Address = VA
Address = VA
I/O
I/O
I/O
START
7
7
FAIL
= Data ?
= Data ?
5
AMIC Technology, Corp.
= 1?
7
7
-I/O
Yes
- I/O
No
No
0
0
A29040B Series
5
Yes
= "1" because
Yes
5
.
PASS