SST25VF032B-80-4I-S2AF SILICON STORAGE TECHNOLOGY, SST25VF032B-80-4I-S2AF Datasheet - Page 5

no-image

SST25VF032B-80-4I-S2AF

Manufacturer Part Number
SST25VF032B-80-4I-S2AF
Description
MEMORY, FLASH, 32MBIT, SPI, 8SOIC
Manufacturer
SILICON STORAGE TECHNOLOGY
Datasheet

Specifications of SST25VF032B-80-4I-S2AF

Memory Size
32Mbit
Clock Frequency
80MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (18-Jun-2010)
Memory Type
Flash
Memory Configuration
4M X 8
Interface Type
Serial, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SST25VF032B-80-4I-S2AF
Manufacturer:
RENESAS
Quantity:
1 182
Part Number:
SST25VF032B-80-4I-S2AF
Manufacturer:
SST/50
Quantity:
2 192
Part Number:
SST25VF032B-80-4I-S2AF
Manufacturer:
SST
Quantity:
543
Part Number:
SST25VF032B-80-4I-S2AF
Manufacturer:
SST
Quantity:
20 000
Company:
Part Number:
SST25VF032B-80-4I-S2AF
Quantity:
2 449
Company:
Part Number:
SST25VF032B-80-4I-S2AF
Quantity:
18 000
A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Memory Organization
Device Operation
The SST25VF032B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable blocks.
The SST25VF032B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF032B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
Figure 3: SPI Protocol
SCK
CE#
SO
SI
MODE 3
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
HIGH IMPEDANCE
5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
32 Mbit SPI Serial Flash
DON T CARE
SST25VF032B
S71327-04-000
MODE 3
MODE 0
Data Sheet
1327 F04.0
02/11

Related parts for SST25VF032B-80-4I-S2AF