SST25VF032B Silicon Storage Technology, Inc., SST25VF032B Datasheet
SST25VF032B
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SST25VF032B Summary of contents
Page 1
... Erase or Program operation is less than alternative flash memory technologies. The SST25VF032B device is offered in both 8-lead SOIC (200 mils) and 16-lead SOIC (300 mils) packages. See Fig- ures 2 and 3 for pin assignments. ...
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... Note AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of- Write Detection” on page 12 for details FIGURE 1: Functional Block Diagram ©2008 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD Mbit SPI Serial Flash SST25VF032B SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1327 B1.0 S71327-01-000 4/08 ...
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... Mbit SPI Serial Flash SST25VF032B PIN DESCRIPTION Notes AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of- Write Detection” on page 12 for details. FIGURE 2: Pin Assignments for 8-Lead SOIC HOLD# Notes AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of- Write Detection” ...
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... The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. V Power Supply To provide power supply voltage: 2.7-3. Ground SS ©2008 Silicon Storage Technology, Inc. 32 Mbit SPI Serial Flash 4 SST25VF032B T1.0 1327 S71327-01-000 4/08 ...
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... Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF032B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 4, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... HOLD# Active FIGURE 5: Hold Condition Waveform Write Protection SST25VF032B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register pro- vide Write protection to the memory array and the status register ...
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... Mbit SPI Serial Flash SST25VF032B Status Register The software status register provides status on whether the flash memory array is available for any Read or Write oper- ation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or TABLE 3: Software Status Register ...
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... Mbit SPI Serial Flash SST25VF032B ), enables the Block-Protection the BPL bit has Protected Memory Address 32 Mbit None 3F0000H-3FFFFFH 3E0000H-3FFFFFH 3C0000H-3FFFFFH 380000H-3FFFFFH 300000H-3FFFFFH 200000H-3FFFFFH 000000H-3FFFFFH T4.0 1327 S71327-01-000 4/08 ...
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... Mbit SPI Serial Flash SST25VF032B INSTRUCTIONS Instructions are used to read, write (Erase and Program), and configure the SST25VF032B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-Enable (WREN) instruction must be executed prior any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Sta- tus-Register, or Chip-Erase instructions ...
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... ADD. ADD. ADD OUT MSB 10 32 Mbit SPI Serial Flash SST25VF032B -A ]. CE# must N+2 N+3 N OUT OUT OUT 1327 F06 ...
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... Mbit SPI Serial Flash SST25VF032B Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a pro- tected memory area will be ignored. ...
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... This is shown in Figure 10 with CE# SCK FIGURE 9: Enable SO as Hardware RY/BY# CE# SCK FIGURE 10: Disable SO as Hardware RY/BY Mbit SPI Serial Flash SST25VF032B MODE MODE MSB HIGH IMPEDANCE SO 1327 F09.0 during AAI Programming MODE MODE 0 ...
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... Mbit SPI Serial Flash SST25VF032B CE MODE 3 SCK MODE Load AAI command, Address, 2 bytes data SO Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming ...
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... Poll the Busy bit in the software status register or wait T for the completion of the internal self-timed Sector-Erase cycle. See Figure 13 for the Sector-Erase sequence ADD. ADD. HIGH IMPEDANCE 14 32 Mbit SPI Serial Flash SST25VF032B -A ]. Address bits [ Most ADD ...
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... Mbit SPI Serial Flash SST25VF032B 32-KByte and 64-KByte Block-Erase The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored ...
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... CE#. See Figure 17 for the RDSR instruction sequence Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB 16 32 Mbit SPI Serial Flash SST25VF032B for the comple Status Register Out 1327 F17.0 S71327-01-000 4/08 ...
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... Mbit SPI Serial Flash SST25VF032B Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- Enable-Latch bit in the Status Register to ‘1’ allowing Write operations to occur. The WREN instruction must be exe- cuted prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Register (WRSR) instruction ...
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... See Table 2 for a summary description of WP# and BPL functions MODE 3 MODE 0 STATUS REGISTER MSB MSB HIGH IMPEDANCE 18 SST25VF032B ) prior to the low-to- IH 1327 F20.0 S71327-01-000 4/08 ...
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... Mbit SPI Serial Flash SST25VF032B Read-ID (RDID) The Read-ID instruction (RDID) identifies the device as SST25VF032B and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A the Read-ID instruction, the manufacturer’ located in address 00000H and the device ID is located in address ...
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... Advance Information JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as SST25VF032B and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 24-bit device ID is shifted out on the SO pin ...
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... Mbit SPI Serial Flash SST25VF032B ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability. Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...
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... T requirements SCKH SCKL 22 32 Mbit SPI Serial Flash SST25VF032B Test Condition Maximum OUT T10.0 1327 Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 T11.0 1327 ...
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... Mbit SPI Serial Flash SST25VF032B CE# T CES T CHH SCK T DS MSB SI HIGH-Z SO FIGURE 23: Serial Input Timing Diagram CE# T SCKH SCK T CLZ SO SI FIGURE 24: Serial Output Timing Diagram ©2008 Silicon Storage Technology, Inc SCKR T SCKL T OH MSB Advance Information T CPH ...
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... All commands are rejected by the device. V Min DD FIGURE 26: Power-up Timing Diagram ©2008 Silicon Storage Technology, Inc HHS HHH HLS T HLH PU-READ Device fully accessible T PU-WRITE 24 32 Mbit SPI Serial Flash SST25VF032B T LZ 1327 F25.0 Time 1327 F26.0 S71327-01-000 4/08 ...
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... Mbit SPI Serial Flash SST25VF032B V IHT INPUT V ILT AC test inputs are driven at V (0.9V IHT for inputs and outputs are V (0.6V HT FIGURE 27: AC Input/Output Reference Waveforms ©2008 Silicon Storage Technology, Inc REFERENCE POINTS for a logic “1” and V (0.1V DD ILT ...
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... XXX X - Valid combinations for SST25VF032B SST25VF032B-66-4C-S2AF SST25VF032B-66-4C-SCF SST25VF032B-66-4I-S2AF SST25VF032B-66-4I-SCF Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ...
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... Mbit SPI Serial Flash SST25VF032B PACKAGING DIAGRAMS Pin #1 Identifier 10.08 10.50 7˚ 4 places .33 .51 Note: 1. Complies with JEDEC publication 95 MS-013 AA dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC min is 10.10; SST min (10.08) is less stringent ‡ = JEDEC min is 0.40; SST min (0.38) is less stringent 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (± ...
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... Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2008 Silicon Storage Technology, Inc. SIDE VIEW 0.50 0.35 1.27 BSC 0.25 0.05 2.16 1.75 0.25 0.19 Description www.SuperFlash.com or www.sst.com 28 32 Mbit SPI Serial Flash SST25VF032B END VIEW 0˚ 8˚ 0.80 0.50 08-soic-EIAJ-S2A-3 1mm Date Oct 2006 Mar 2008 S71327-01-000 4/08 ...