SST25VF040B-50-4I-S2AF SILICON STORAGE TECHNOLOGY, SST25VF040B-50-4I-S2AF Datasheet - Page 10

• Manufacturer Part Number: SST25VF040B-50-4I-S2AF
• Description: 4M FLASH MEMORY, SPI EEPROM, SOIC8
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25VF040B-50-4I-S2AF

• Memory Size: 4Mbit
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Svhc: No SVHC (18-Jun-2010)
• Device: RoHS Compliant
• Package / Case: SOIC
• Memory Type: Flash
• Memory Configuration: 512K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes

Data Sheet
High-Speed-Read (50 MHz)
The High-Speed-Read instruction supporting up to 50 MHz
Read is initiated by executing an 8-bit command, 0BH, fol-
lowed by address bits [A
must remain active low for the duration of the High-Speed-
Read cycle. See Figure 5 for the High-Speed-Read
sequence.
Following a dummy cycle, the High-Speed-Read instruc-
tion outputs the data starting from the specified address
location. The data output stream is continuous through all
©2006 Silicon Storage Technology, Inc.
SCK
CE#
FIGURE 5: H
SO
SI
MODE 3
MODE 0
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
MSB
0 1 2 3 4 5 6 7 8
IGH
-S
PEED
23
0B
-A
0
-R
] and a dummy byte. CE#
HIGH IMPEDANCE
EAD
S
EQUENCE
MSB
ADD.
15 16
ADD.
23 24
ADD.
10
IL
or V
31 32
addresses until terminated by a low to high transition on
CE#. The internal address pointer will automatically incre-
ment until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer will automatically increment to the beginning (wrap-
around) of the address space. Once the data from address
location 7FFFFH has been read, the next output will be
from address location 00000H.
IH
)
X
39 40
MSB
D
OUT
N
47 48
D
N+1
OUT
4 Mbit SPI Serial Flash
55 56
D
N+2
OUT
63 64
SST25VF040B
D
N+3
OUT
S71295-01-000
71 72
1295 HSRdSeq.0
D
N+4
OUT
80
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