SST25VF080B-80-4I-QAE SILICON STORAGE TECHNOLOGY, SST25VF080B-80-4I-QAE Datasheet - Page 9

• Manufacturer Part Number: SST25VF080B-80-4I-QAE
• Description: MEMORY, FLASH, 8MBIT, SPI, 8WSON
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25VF080B-80-4I-QAE

• Memory Size: 8Mbit
• Clock Frequency: 80MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: WSON
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Memory Type: Flash
• Memory Configuration: 1M X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25VF080B. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-
Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed
first. The complete list of instructions is provided in Table 5. All instructions are synchronized off a high
to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most signif-
icant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Instruction
Read
High-Speed Read
4 KByte Sector-Erase
32 KByte Block-Erase
64 KByte Block-Erase
Chip-Erase
Byte-Program
AAI-Word-Program
RDSR
EWSR
WRSR
WREN
WRDI
RDID
JEDEC-ID
EBSY
DBSY
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit of each density can be V
3. 4KByte Sector Erase addresses: use A
4. 32KByte Block Erase addresses: use A
5. 64KByte Block Erase addresses: use A
8
7
6
3
4
5
Description
Read Memory
Read Memory at higher
speed
Erase 4 KByte of
memory array
Erase 32 KByte block
of memory array
Erase 64 KByte block
of memory array
Erase Full Memory Array
To Program One Data Byte
Auto Address Increment
Programming
Read-Status-Register
Enable-Write-Status-Register 0101b 0000b (50H)
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
JEDEC ID read
Enable SO to output RY/BY#
status during AAI programming
Disable SO as RY/BY#
status during AAI programming
MS
MS
MS
-A
-A
-A
9
12,
15,
16,
remaining addresses are don’t care but must be set either at V
remaining addresses are don’t care but must be set either at V
remaining addresses are don’t care but must be set either at V
Op Code Cycle
0000 0011b (03H)
0000 1011b (0BH)
0010 0000b (20H)
0101 0010b (52H)
1101 1000b (D8H)
0110 0000b (60H) or
1100 0111b (C7H)
0000 0010b (02H)
1010 1101b (ADH)
0000 0101b (05H)
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H) or
1010 1011b (ABH)
1001 1111b (9FH)
0111 0000b (70H)
1000 0000b (80H)
8 Mbit SPI Serial Flash
IL
or V
IH
1
.
Cycle(s)
Address
3
3
3
3
3
0
3
3
0
0
0
0
0
3
0
0
0
SST25VF080B
2
Cycle(s)
Dummy
S71296-05-000
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Sheet
Cycle(s)
IL
IL
IL
1 to ∞
1 to ∞
2 to ∞
1 to ∞
1 to ∞
3 to ∞
T5.0 1296
or V
Data
or V
or V
0
0
0
0
1
0
1
0
0
0
0
IH.
IH.
IH.
02/11