AM29F160DT-75EF Spansion Inc., AM29F160DT-75EF Datasheet - Page 20

• Manufacturer Part Number: AM29F160DT-75EF
• Description: IC, FLASH, 16MBIT, 75NS, TSOP-48
• Manufacturer: Spansion Inc.

Specifications of AM29F160DT-75EF

• Memory Type: Flash
• Memory Size: 16Mbit
• Memory Configuration: 2M X 8 / 1M X 16
• Ic Interface Type: Parallel
• Access Time: 75ns
• Supply Voltage Range: 4.75V To 5.25V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 4.75 to 5.25V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during V
power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See
pend/Erase Resume Commands‚ on page 21
information on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
18
CC
CC
Write Inhibit
is less than V
LKO
. The system must provide the
LKO
, the device does not ac-
CC
power-up and
Erase Sus-
for more
D A T A S H E E T
Am29F160D
CC
CC
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
or while in the autoselect mode. See the
mand‚ on page 18
See also
page 8
table provides the read parameters, and Read Opera-
tion Timings diagram shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
IL
, CE# = V
for more information. The Read Operations
Requirements for Reading Array Data‚ on
IH
or WE# = V
IL
section, next.
and OE# = V
CC
Am29F160D_00_D10 April 23, 2010
is greater than V
IH
. To initiate a write cycle,
IH
during power up, the
LKO
Reset Com-
.