AM29F160DT-75EF Spansion Inc., AM29F160DT-75EF Datasheet - Page 26

• Manufacturer Part Number: AM29F160DT-75EF
• Description: IC, FLASH, 16MBIT, 75NS, TSOP-48
• Manufacturer: Spansion Inc.

Specifications of AM29F160DT-75EF

• Memory Type: Flash
• Memory Size: 16Mbit
• Memory Configuration: 2M X 8 / 1M X 16
• Ic Interface Type: Parallel
• Access Time: 75ns
• Supply Voltage Range: 4.75V To 5.25V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 4.75 to 5.25V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 10 on page 26
The timing diagrams for read, reset, program, and
erase shows the relationship of RY/BY# to other sig-
nals.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on
page
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
24
23).
CC
.
shows the outputs for RY/BY#.
DQ7: Data# Polling‚ on
D A T A S H E E T
Am29F160D
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to
the toggle bit algorithm, and to the Toggle Bit Timings
figure in the “AC Characteristics” section for the timing
diagram. The DQ2 vs. DQ6 figure shows the differ-
ences between DQ2 and DQ6 in graphical form. See
also the subsection on
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that were selected for erasure.
(The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both sta-
tus bits are required for sector and mode information.
Refer to
DQ2 and DQ6.
Figure 6, on page 25
flowchart form, and the section
plains the algorithm. See also the
subsection. Refer to the Toggle Bit Timings figure for
the toggle bit timing diagram. The DQ2 vs. DQ6 figure
shows the differences between DQ2 and DQ6 in graph-
ical form.
Reading Toggle Bits DQ6/DQ2
Refer to
sion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice
in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of
the toggle bit after the first read. After the second
read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling,
the device completed the program or erase operation.
The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
Figure 6, on page 25
Table 10 on page 26
shows the toggle bit algorithm in
Am29F160D_00_D10 April 23, 2010
DQ2: Toggle Bit II‚ on page
Figure 6, on page 25
for the following discus-
to compare outputs for
“DQ2: Toggle Bit II”
“DQ6: Toggle Bit I”
24.
ex-
for