LPC2468FBD208 NXP Semiconductors, LPC2468FBD208 Datasheet - Page 4

• Manufacturer Part Number: LPC2468FBD208
• Description: IC, 32BIT MCU, ARM7, 72MHZ, LQFP-208
• Manufacturer: NXP Semiconductors

Specifications of LPC2468FBD208

• Controller Family/series: (ARM7)
• No. Of I/o's: 160
• Ram Memory Size: 98KB
• Cpu Speed: 72MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 12
• Core Size: 32 Bit
• Program Memory Size: 512KB
• Rohs Compliant: Yes
• Oscillator Type: External, Internal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
5. Block diagram
LPC2468
Product data sheet
Fig 1.
6 × PWM0/PWM1
2 × CAP0/CAP1/
4 × MAT2/MAT3,
EINT3 to EINT0
power domain 2
CAP2/CAP3
1 × PCAP0,
2 × PCAP1
P0, P1, P2,
2 × MAT0,
3 × MAT1
LPC2468 block diagram
MII/RMII
8 × AD0
ALARM
RTCX1
RTCX2
P0, P2
P0, P1
AOUT
P3, P4
VBAT
HIGH-SPEED
ETHERNET
LPC2468
MAC WITH
OSCILLATOR
160 PINS
DMA
GPIO
TOTAL
EXTERNAL INTERRUPTS
RTC
CAPTURE/COMPARE
2 kB BATTERY RAM
SYSTEM CONTROL
WATCHDOG TIMER
A/D CONVERTER
D/A CONVERTER
TIMER0/TIMER1/
TIMER2/TIMER3
LEGACY GPI/O
64 PINS TOTAL
PWM0, PWM1
AHB2
SRAM
SRAM
16 kB
64 kB
CONTROLLERS
SRAM
INTERNAL
CLOCK
REAL-
TIME
All information provided in this document is subject to legal disclaimers.
FLASH
512 kB
FLASH
BRIDGE
MASTER
PORT
TRST
AHB
Rev. 5 — 15 October 2010
ARM7TDMI-S
TMS
TEST/DEBUG
INTERFACE
TCK TDO
APB BRIDGE
APB BRIDGE
AHB TO
TDI
AHB TO
EXTIN0
trace signals
BRIDGE
AHB
SLAVE
PORT
DBGEN
VIC
system
clock
PLL
SPI, SSP0 INTERFACE
UART0, UART2, UART3
RESET
SRAM
SSP1 INTERFACE
16 kB
SD/MMC CARD
I
I
4 kB RAM AND DMA
2
2
HOST/OTG WITH
CAN1, CAN2
S INTERFACE
INTERFACE
C0, I
USB DEVICE/
XTAL2
CONTROLLER
UART1
INTERNAL RC
OSCILLATOR
AHB1
FUNCTIONS
2
GP DMA
C1, I
CONTROLLER
XTAL1
SYSTEM
EXTERNAL
Single-chip 16-bit/32-bit micro
MEMORY
2
C2
V
DDA
002aac721
V
DD(3V3)
V
DD(1V8)
LPC2468
© NXP B.V. 2010. All rights reserved.
A[23:0]
control lines
V
port1
port2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL1
SCK1
MOSI1
MIS01
SSEL1
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1
RXD1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
VREF
V
V
V
D[31:0]
BUS
SSA
SSCORE
DD(DCDC)(3V3)
, V
SSIO,
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