PIC16LF874A-I/PT Microchip Technology, PIC16LF874A-I/PT Datasheet - Page 50
![IC, 8BIT MCU, PIC16LF, 20MHZ, TQFP-44](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC16LF874A-I/PT
Manufacturer Part Number
PIC16LF874A-I/PT
Description
IC, 8BIT MCU, PIC16LF, 20MHZ, TQFP-44
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF874A-I/PT
Controller Family/series
PIC16LF
No. Of I/o's
33
Eeprom Memory Size
128Byte
Ram Memory Size
192Byte
Cpu Speed
20MHz
No. Of Timers
3
Core Size
8 Bit
Program Memory Size
4 Kwords
Core Processor
PIC
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F87XA
4.4
PORTD is an 8-bit port with Schmitt Trigger input
buffers. Each pin is individually configurable as an input
or output.
PORTD can be configured as an 8-bit wide
microprocessor port (Parallel Slave Port) by setting
control bit, PSPMODE (TRISE<4>). In this mode, the
input buffers are TTL.
TABLE 4-7:
TABLE 4-8:
DS39582B-page 48
08h
88h
89h
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1:
Address
Note:
Name
PORTD and TRISD Registers
PORTD
TRISD
TRISE
Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
PORTD and TRISD are not implemented
on the 28-pin devices.
Name
Bit#
bit 0
bit 1
bit 3
bit 4
bit 5
bit 6
bit 7
bit2
PORTD FUNCTIONS
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
PORTD Data Direction Register
Bit 7
RD7
IBF
Bit 6
RD6
OBF IBOV PSPMODE
Buffer Type
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
Bit 5
RD5
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Bit 4
RD4
Input/output port pin or Parallel Slave Port bit 0.
Input/output port pin or Parallel Slave Port bit 1.
Input/output port pin or Parallel Slave Port bit 2.
Input/output port pin or Parallel Slave Port bit 3.
Input/output port pin or Parallel Slave Port bit 4.
Input/output port pin or Parallel Slave Port bit 5.
Input/output port pin or Parallel Slave Port bit 6.
Input/output port pin or Parallel Slave Port bit 7.
Bit 3
RD3
—
FIGURE 4-8:
PORTE Data Direction Bits 0000 -111 0000 -111
Bit 2
RD2
Note 1: I/O pins have protection diodes to V
Data
Bus
WR
Port
WR
TRIS
RD
TRIS
RD Port
Bit 1
RD1
TRIS Latch
Function
Data Latch
D
D
CK
CK
Q
Bit 0
RD0
Q
PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
2003 Microchip Technology Inc.
Q
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
POR, BOR
Value on:
EN
EN
Schmitt
Trigger
Input
Buffer
D
DD
and V
Value on
all other
I/O pin
Resets
SS
.
(1)
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