PIC18F46K20-E/P Microchip Technology, PIC18F46K20-E/P Datasheet - Page 163
![IC, 8BIT MCU, PIC18F, 64MHZ, DIP-40](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F46K20-E/P
Manufacturer Part Number
PIC18F46K20-E/P
Description
IC, 8BIT MCU, PIC18F, 64MHZ, DIP-40
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
Specifications of PIC18F46K20-E/P
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
1024Byte
Ram Memory Size
3936Byte
Cpu Speed
64MHz
No. Of Timers
4
Core Size
8 Bit
Program Memory Size
32768 Words
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 14 Channel
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F46K20-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F26K20-ISS PDF datasheet #3
- PIC18F26K20-ISS PDF datasheet #4
- Current page: 163 of 456
- Download datasheet (4Mb)
13.6.2
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
When the LPT1OSC Configuration bit of the
CONFIG3H register is set, the Timer1 oscillator oper-
ates in a low-power mode. When LPT1OSC is not set,
Timer1 operates at a higher power level. Power con-
sumption for a particular mode is relatively constant,
regardless of the device’s operating mode. The default
Timer1 configuration is the higher power mode.
As the low-power Timer1 mode tends to be more
sensitive to interference, high noise environments may
cause some oscillator instability. The low-power option is,
therefore, best suited for low noise applications where
power conservation is an important design consideration.
13.6.3
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 13-4, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than V
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 13-5, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 13-5:
2010 Microchip Technology Inc.
Note: Not drawn to scale.
LOW-POWER TIMER1 OPTION
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
SS
V
OSC1
OSC2
RC0
RC1
V
RC2
or V
DD
SS
DD
.
13.7
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in the TMR1IF interrupt flag bit of the
PIR1 register. This interrupt can be enabled or disabled
by setting or clearing the TMR1IE Interrupt Enable bit
of the PIE1 register.
13.8
If either of the CCP modules is configured to use Timer1
and generate a Special Event Trigger in Compare mode
(CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will
reset Timer1. The trigger from CCP2 will also start an
A/D conversion if the A/D module is enabled (see
Section 11.3.4 “Special Event Trigger” for more
information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special Event Trigger, the write operation will take
precedence.
PIC18F2XK20/4XK20
Note:
Timer1 Interrupt
Resetting Timer1 Using the CCP
Special Event Trigger
The Special Event Triggers from the CCP2
module will not set the TMR1IF interrupt
flag bit of the PIR1 register.
DS41303G-page 163
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