LPC1112FHN33/201 NXP Semiconductors, LPC1112FHN33/201 Datasheet - Page 22

• Manufacturer Part Number: LPC1112FHN33/201
• Description: MCU, 32BIT, 16KFLASH, CORTEX-M0, 33HVQFN
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/201

• Controller Family/series: ARM Cortex-M0
• No. Of I/o's: 28
• Ram Memory Size: 4KB
• Cpu Speed: 50MHz
• No. Of Timers: 4
• Core Size: 32bit
• Program Memory Size: 16KB
• Oscillator Type: External, Internal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1111_12_13_14
Product data sheet
7.5.2 Interrupt sources
7.7.1 Features
7.6 IOCONFIG block
7.7 Fast general purpose parallel I/O
7.8 UART
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be
programmed to generate an interrupt on a level, or rising edge or falling edge, or both.
The IOCONFIG block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC1111/12/13/14 use accelerated GPIO functions:
Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
The LPC1111/12/13/14 contain one UART.
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In the LPC1111/12/13/14, the NVIC supports 32 vectored interrupts including up to 13
inputs to the start logic from individual GPIO pins.
Four programmable interrupt priority levels with hardware priority level masking.
Software interrupt generation.
GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
Entire port value can be written in one instruction.
Bit level port registers allow a single instruction to set or clear any number of bits in
one write operation.
Direction control of individual bits.
All I/O default to inputs with pull-ups enabled after reset with the exception of the
I
Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG
block for each GPIO pin (except for pins PIO0_4 and PIO0_5).
2
C-bus pins PIO0_4 and PIO0_5.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 10 February 2011
32-bit ARM Cortex-M0 microcontroller
LPC1111/12/13/14
© NXP B.V. 2011. All rights reserved.
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