LPC1227FBD64/301 NXP Semiconductors, LPC1227FBD64/301 Datasheet - Page 27

• Manufacturer Part Number: LPC1227FBD64/301
• Description: MCU, 128K FLASH, CORTEX-M0, 64LQFP
• Manufacturer: NXP Semiconductors

Specifications of LPC1227FBD64/301

• Rohs Compliant: YES
• Featured Product: LPC122x Cortex-M0 Microcontrollers
• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 45MHz
• Connectivity: I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 55
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: LPC1200
• No. Of I/o's: 55
• Ram Memory Size: 8KB
• Cpu Speed: 30MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-5164; LPC1227FBD64/301

NXP Semiconductors
LPC122X
Objective data sheet
CAUTION
7.19.3 Brownout detection
7.19.4 Code security (Code Read Protection - CRP)
7.19.5 APB interface
7.19.6 AHB-Lite
7.19.7 External interrupt inputs
An external pull-up resistor is required on the RESET pin if Deep power-down mode is
used.
The LPC122x includes four levels for monitoring the voltage on the V
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register. An additional threshold level can be selected to cause a
forced reset of the chip.
This feature of the LPC122x allows user to enable different levels of security in the system
so that access to the on-chip flash and use of the SWD and ISP can be restricted. When
needed, CRP is invoked by programming a specific pattern into a dedicated flash location.
IAP commands are not affected by the CRP.
There are three levels of Code Read Protection:
In addition to the three CRP levels, sampling of pin PIO0_12 for valid user code can be
disabled.
The APB peripherals are located on one APB bus.
The AHB-Lite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs.
1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding
2. CRP2 disables access to chip via the SWD and only allows full flash erase and
3. Running an application with level CRP3 selected fully disables any access to chip via
flash sector 0) using a limited set of the ISP commands. This mode is useful when
CRP is required and flash field updates are needed but all sectors can not be erased.
update using a reduced set of the ISP commands.
the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_12
pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
UART0.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 29 March 2011
32-bit ARM Cortex-M0 microcontroller
DD(3V3)
LPC122x
© NXP B.V. 2011. All rights reserved.
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