LPC2104BBD48.151 NXP Semiconductors, LPC2104BBD48.151 Datasheet - Page 9

• Manufacturer Part Number: LPC2104BBD48.151
• Description: IC, 32BIT MCU, ARM7, 60MHZ, LQFP-48
• Manufacturer: NXP Semiconductors

Specifications of LPC2104BBD48.151

• Controller Family/series: (ARM7)
• No. Of I/o's: 32
• Ram Memory Size: 16KB
• Cpu Speed: 60MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 6
• Core Size: 32 Bit
• Program Memory Size: 128KB
• Embedded Interface Type: I2C, JTAG, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 3.
[1]
[2]
[3]
[4]
[5]
LPC2104_2105_2106_7
Product data sheet
Symbol
P0.26/TRACESYNC
P0.27/TRACEPKT0/
TRST
P0.28/TRACEPKT1/
TMS
P0.29/TRACEPKT2/
TCK
P0.30/TRACEPKT3/
TDI
P0.31/EXTIN0/TDO
RTCK
DBGSEL
RESET
XTAL1
XTAL2
V
V
V
n.c.
SS
DD(1V8)
DD(3V3)
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
Open-drain 5 V tolerant digital I/O pad, compatible with I
functionality. Open-drain configuration applies to all functions on this pin.
SSP interface available on LPC2104/2105/2106/01 only.
5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
The pull-up resistor’s value ranges from 60 k to 300 k .
5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
Pin description
Pin
39
8
9
10
15
16
26
27
6
11
12
7, 19,
31, 43
5
17, 40
4, 20,
25, 42
[4]
[4]
[5]
[4]
[4]
[4]
[4]
[4]
…continued
Type
I/O
O
I/O
O
I
I/O
O
I
I/O
O
I
I/O
O
I
I/O
I
O
I/O
I
I
I
O
I
I
I
-
Description
P0.26 — Port 0 bit 26.
TRACESYNC — Trace Synchronization Standard I/O port with internal pull-up.
P0.27 — Port 0 bit 27.
TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.
TRST — Test Reset for JTAG interface, secondary JTAG pin group.
P0.28 — Port 0 bit 28.
TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.
TMS — Test Mode Select for JTAG interface, secondary JTAG pin group.
P0.29 — Port 0 bit 29.
TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.
TCK — Test Clock for JTAG interface, secondary JTAG pin group. This clock
must be slower than 1/6 of the CPU clock (CCLK) for the JTAG interface to
operate.
P0.30 — Port 0 bit 30.
TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.
TDI — Test Data In for JTAG interface, secondary JTAG pin group.
P0.31 — Port 0 bit 31.
EXTIN0 — External Trigger Input. Standard I/O port with internal pull-up.
TDO — Test Data out for JTAG interface, secondary JTAG pin group.
Returned Test Clock output: Extra signal added to the JTAG port. Assists
debugger synchronization when processor frequency varies. Also used during
debug mode entry to select primary or secondary JTAG pins with the 48-pin
package. Bidirectional pin with internal pull-up.
Debug Select: When LOW, the part operates normally. When HIGH, debug
mode is entered. Input pin with internal pull-down.
external reset input; a LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
input to the oscillator circuit and internal clock generator circuits.
output from the oscillator amplifier.
ground: 0 V reference.
1.8 V core power supply; this is the power supply voltage for internal circuitry.
3.3 V pad power supply; this is the power supply voltage for the I/O ports.
not connected; these pins are not connected in the 48-pin package.
Rev. 07 — 20 June 2008
2
C-bus 400 kHz specification. It requires external pull-up to provide an output
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
© NXP B.V. 2008. All rights reserved.
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