LPC2106FBD48/01 NXP Semiconductors, LPC2106FBD48/01 Datasheet - Page 22

• Manufacturer Part Number: LPC2106FBD48/01
• Description: IC, MCU, 32BIT, 128K FLASH, 48LQFP
• Manufacturer: NXP Semiconductors

Specifications of LPC2106FBD48/01

• Controller Family/series: ARM7
• No. Of I/o's: 32
• Ram Memory Size: 64KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• No. Of Pwm: RoHS Compliant
• Core Size: 32bit
• Program Memory Size: 128KB
• Oscillator Type: Internal, External

NXP Semiconductors
LPC2104_2105_2106_7
Product data sheet
6.18.3 Reset and wake-up timer
6.18.4 Code security (Code Read Protection - CRP)
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed
following a chip Reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100 s.
Reset has two sources on the LPC2104/2105/2106: the RESET pin and Watchdog Reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip Reset by any source starts the wake-up timer (see wake-up timer description below),
causing the internal chip reset to remain asserted until the external Reset is de-asserted,
the oscillator is running, a fixed number of clocks have passed, and the on-chip flash
controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is the Reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of Reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
This feature of the LPC2104/2105/2106/01 allows the user to enable different levels of
security in the system so that access to the on-chip flash and use of the JTAG and ISP
can be restricted. When needed, CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection:
1. CRP1 disables access to the chip via the JTAG and allows partial flash update
2. CRP2 disables access to the chip via the JTAG and only allows full flash erase and
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
update using a reduced set of the ISP commands.
Rev. 07 — 20 June 2008
DD
ramp (in the case of power on), the type of crystal
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
© NXP B.V. 2008. All rights reserved.
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