LPC2131FBD64 NXP Semiconductors, LPC2131FBD64 Datasheet - Page 24

• Manufacturer Part Number: LPC2131FBD64
• Description: 16/32BIT MCU ARM7, 32K FLASH, 64LQFP
• Manufacturer: NXP Semiconductors

Specifications of LPC2131FBD64

• No. Of I/o's: 47
• Ram Memory Size: 8KB
• Cpu Speed: 60MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 6
• Digital Ic Case: RoHS Compliant
• Core Size: 32bit
• Program Memory Size: 32KB
• Oscillator Type: External Only
• Controller Family/series: LPC21xx
• Rohs Compliant: Yes

NXP Semiconductors
LPC2131_32_34_36_38
Product data sheet
6.18.8 Power Control
6.18.9 APB bus
6.19.1 EmbeddedICE
6.19 Emulation and debugging
The LPC2131/32/34/36/38 support two reduced power modes: Idle mode and
Power-down mode.
In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.
Peripheral functions continue operation during Idle mode and may generate interrupts to
cause the processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip
RTC will enable the microcontroller to have the RTC active during Power-down mode.
Power-down current is increased with RTC active. However, it is significantly lower than in
Idle mode.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB bus so that they can operate at
the speed chosen for the ARM processor. In order to achieve this, the APB bus may be
slowed down to
properly at power-up (and its timing cannot be altered if it does not work since the APB
divider control registers reside on the APB bus), the default condition at reset is for the
APB bus to run at
is to allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the APB divider is connected to the PLL output, the PLL
remains active (if it was running) during Idle mode.
The LPC2131/32/34/36/38 support emulation and debugging via a JTAG serial port. A
trace port allows tracing program execution. Debugging and trace functions are
multiplexed only with GPIOs on Port 1. This means that all communication, timer and
interface peripherals residing on Port 0 are available during the development and
debugging phase as they are when the application is run in the embedded system itself.
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.
All information provided in this document is subject to legal disclaimers.
1
⁄
2
1
to
⁄
4
of the processor clock rate. The second purpose of the APB divider
1
⁄
Rev. 5 — 2 February 2011
4
of the processor clock rate. Because the APB bus must work
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
© NXP B.V. 2011. All rights reserved.
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