ECOG1X14Z5 CYAN, ECOG1X14Z5 Datasheet - Page 19

• Manufacturer Part Number: ECOG1X14Z5
• Description: IC, 16BIT MCU, ECOG1X, 70MHZ, BGA-208
• Manufacturer: CYAN

Specifications of ECOG1X14Z5

• Controller Family/series: ECOG1X
• No. Of I/o's: 120
• Ram Memory Size: 24KB
• Cpu Speed: 70MHz
• No. Of Timers: 14
• No. Of Pwm Channels: 8
• Core Size: 16 Bit
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Description
CPU
Instruction Set
4 August 2009
This section gives a brief description of the main features of the eCOG1X device family. For a
complete description, see the eCOG1X User Manual.
The eCOG1X has an advanced high speed, low
power CPU with an instruction set targeted at high
level languages, in particular C. The CPU operates at
internal clock frequencies up to 70MHz. Full details of
the instruction set are contained in the eCOG1 Macro
Assembler User Manual.
The main features of the processor are:
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The eCOG1 instruction set includes 42 instructions with 6 addressing modes. Most instructions
operate on 16-bit word data values, while the LD and ST instructions also have variants for handling
byte data values.
16-bit RISC.
Sleep mode to support low power applications.
Harvard architecture (separate internal address
and data buses for faster memory accesses).
16-bit data space addressing range
(64K by 16 bits).
24-bit code space addressing range
(16M by 16 bits).
Support for debugging and multiple breakpoints.
Single level of interrupt.
Powerful mathematical functions including:
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Address mode
Immediate
Direct
Indexed X
Indexed Y
Address mode
PC relative
X relative
Direct
Indexed Y
16 by 16 signed and unsigned multiply.
32 by 16 unsigned divide.
Single cycle barrel shifter.
eCOG and CyanIDE are registered trademarks of Cyan Holdings plc
eCOG1X Microcontroller Product Family
Table 14: Branch addressing modes
#arg
Syntax
@arg
@(arg,x)
@(arg,y)
Syntax
arg
arg,x
@arg
@(arg,y)
Table 13: Data addressing modes
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Data address
arg
Contents of address (arg)
Contents of address (arg + X reg)
Contents of address (arg + Y reg)
Branch address (new PC value)
PC + arg
XH:X + arg
XH:contents of address (arg)
XH:contents of address (arg + Y reg)
Version 1.15
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