ST7FLITE05Y0B6 FARNELL, ST7FLITE05Y0B6 Datasheet - Page 89
ST7FLITE05Y0B6
Manufacturer Part Number
ST7FLITE05Y0B6
Description
IC, 8BIT MCU, ST7, 16MHZ, DIP-16
Manufacturer
FARNELL
Datasheet
1.ST7FLITE05Y0B6.pdf
(124 pages)
Specifications of ST7FLITE05Y0B6
Controller Family/series
ST7
No. Of I/o's
13
Ram Memory Size
128Byte
Cpu Speed
16MHz
No. Of Timers
2
Interface
SPI
Core Size
8 Bit
Program Memory Size
1.5 Kb
Peripherals
ADC, PWM, Timer
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITE05Y0B6
Manufacturer:
ST
Quantity:
20 000
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13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
13.4.1 Supply Current
T
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at V
driven by external square wave, LVD disabled.
3. SLOW mode selected with f
V
4. SLOW-WAIT mode selected with f
V
5. All I/O pins in output mode with a static value at V
tested in production at V
Figure 56. Typical I
Symbol
SS
DD
A
I
DD
= -40 to +85°C unless otherwise specified
5.0
4.0
3.0
2.0
1.0
0.0
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
or V
SS
2.4
Supply current in RUN mode
Supply current in WAIT mode
Supply current in SLOW mode
Supply current in SLOW WAIT mode
Supply current in HALT mode
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
8MHz
4MHz
1MHz
2.7
DD
Parameter
DD
3.7
Vdd (V)
in RUN vs. f
max and f
CPU
4.5
based on f
CPU
CPU
5
5)
CPU
based on f
max.
OSC
5.5
divided by 32. All I/O pins in input mode with a static value at V
DD
SS
OSC
or V
(no load), LVD disabled. Data based on characterization results,
divided by 32. All I/O pins in input mode with a static value at
f
f
f
f
-40°C≤T
-40°C≤T
T
SS
CPU
CPU
CPU
CPU
A
= +85°C
(no load), all peripherals in reset state; clock input (CLKIN)
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
Figure 57. Typical I
=8MHz
=8MHz
=250kHz
=250kHz
Conditions
A
A
≤+85°C
≤+105°C
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
1)
2)
3)
4)
2.4
250kHz
125kHz
62.5kHz
ST7LITE0xY0, ST7LITESxY0
2.7
DD
DD
or V
in SLOW vs. f
3.7
Vdd (V)
SS
4.50
1.75
0.75
0.65
0.50
TBD
Typ
(no load), all peripherals
5
4.5
7.00
2.70
1.13
1
10
TBD
100
Max
5
CPU
5.5
89/124
Unit
mA
µA
DD
or
1
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