ST7FLITE05Y0B6 FARNELL, ST7FLITE05Y0B6 Datasheet - Page 94
ST7FLITE05Y0B6
Manufacturer Part Number
ST7FLITE05Y0B6
Description
IC, 8BIT MCU, ST7, 16MHZ, DIP-16
Manufacturer
FARNELL
Datasheet
1.ST7FLITE05Y0B6.pdf
(124 pages)
Specifications of ST7FLITE05Y0B6
Controller Family/series
ST7
No. Of I/o's
13
Ram Memory Size
128Byte
Cpu Speed
16MHz
No. Of Timers
2
Interface
SPI
Core Size
8 Bit
Program Memory Size
1.5 Kb
Peripherals
ADC, PWM, Timer
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITE05Y0B6
Manufacturer:
ST
Quantity:
20 000
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ST7LITE0xY0, ST7LITESxY0
EMC CHARACTERISTICS (Cont’d)
13.7.3 Absolute Maximum Ratings (Electrical
Sensitivity)
Based on two different tests (ESD and LU) using
specific measurement methods, the product is
stressed in order to determine its performance in
terms of electrical sensitivity.
ESD absolute maximum ratings
Notes:
1. Data based on characterization results, not tested in production.
13.7.3.2 Static Latch-Up
■
Electrical Sensitivities
Note:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
94/124
1
V
LU: Two complementary static tests are
required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to
each power supply pin) and a current injection
Symbol
Symbol
ESD(HBM)
LU
Electro-static discharge voltage
(Human Body Model)
Static latch-up class
Parameter
Ratings
T
conforming to JESD22-A114
T
conforming to JESD78A
A
A
=+25°C
=+25°C
13.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). This test conforms to the JESD22-
A114A standard.
(applied to each input, output and configurable I/
O pin) are performed on each sample. These
test are compliant with the EIA/JESD 78 IC
latch-up standard.
Conditions
Conditions
Maximum value
4000
II level A
Class
1)
1)
Unit
V
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