ST7FLITE09Y0B6 FARNELL, ST7FLITE09Y0B6 Datasheet - Page 40

• Manufacturer Part Number: ST7FLITE09Y0B6
• Description: IC, 8BIT MCU, ST7, 16MHZ, DIP-16
• Manufacturer: FARNELL

Specifications of ST7FLITE09Y0B6

• Controller Family/series: ST7
• No. Of I/o's: 13
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Core Size: 8 Bit
• Program Memory Size: 1.5 Kb
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE0xY0, ST7LITESxY0
POWER SAVING MODES (Cont’d)
9.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when active halt mode is disa-
bled.
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 6, “Interrupt
Mapping,” on page 30) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
CPU cycle delay is used to stabilize the oscillator.
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up (see
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
tion 15.1 on page 112
Figure 27. HALT Timing Overview
40/124
1
[Active Halt disabled]
INSTRUCTION
RUN
HALT
HALT
256 CPU CYCLE
INTERRUPT
for more details).
RESET
DELAY
OR
Figure
VECTOR
FETCH
RUN
28).
sec-
Figure 28. HALT Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 6, “Interrupt Mapping,” on page 30 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
5. If the PLL is enabled by option byte, it outputs
the clock after a delay of t
N
HALT INSTRUCTION
(Active Halt disabled)
WATCHDOG
WDGHALT
RESET
1
INTERRUPT
Y
1)
3)
ENABLE
OR SERVICE INTERRUPT
0
256 CPU CLOCK CYCLE
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
CPU
I BIT
CPU
I BIT
CPU
I BITS
STARTUP
N
DELAY
RESET
Y
WATCHDOG
(see
DISABLE
Figure
2)
OFF
OFF
OFF
OFF
ON
ON
X
ON
ON
ON
X
0
4)
4)
13).