ST7FLITE09Y0B6 FARNELL, ST7FLITE09Y0B6 Datasheet - Page 60

• Manufacturer Part Number: ST7FLITE09Y0B6
• Description: IC, 8BIT MCU, ST7, 16MHZ, DIP-16
• Manufacturer: FARNELL

Specifications of ST7FLITE09Y0B6

• Controller Family/series: ST7
• No. Of I/o's: 13
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Core Size: 8 Bit
• Program Memory Size: 1.5 Kb
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE0xY0, ST7LITESxY0
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 38. Single Master/ Single Slave Application
60/124
1
38.
MSBit
8-BIT SHIFT REGISTER
GENERATOR
CLOCK
SPI
MASTER
LSBit
MOSI
SCK
SS
MISO
+5V
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see
must be programmed with the same timing mode.
MOSI
MISO
SCK
SS
Figure
8-BIT SHIFT REGISTER
MSBit
Not used if SS is managed
by software
41) but master and slave
SLAVE
LSBit